@Peter Clarke: thanks for the article and the follow up answers. You hit the nail on the head as to who should foot the bill to develop hardware like steppers, even wafer carriers, etc. It is no small feat to manage 450mm wafers if they are going to be thinned for stacking (which is becoming increasingly common for xDIMM's).
Small fab hardware companies have been burnt by trying to dance with Intel (experience speaking here!) so just a promise of 'opportunity' is NOT going to cut it!
The node labels are indeed confusing -one runs into 30nm along with 28nm, etc., they use the same equipment; Samsung's nomenclature makes sense!
In reply to earlier questions about why Intel does not move to production on 450-mm wafers now.
This is because there is no production equipment able to support this. There are precious few standards for 450-mm wafers, FOUPS and equipment, and a large amount of research and development work remains to be done.
As one reader above said, there is still a question mark over who should foot the bill for this work.
In an ideal world a set of ambitious chipmaking equipment providers might do the work, so they can benefit from Intel purchase orders in times to come. But collectively spending billions of dollars in the hope that Intel will follow their lead is not attractive. Especially as those same manufacturers have already gone down this road for such developments as EUV lithography and have yet to see the orders.
As to the labels slipping, you are quite right. And they have been since about 500-nanometers (500-nm) when people first started asking whether the node measure was of the minimum geometry as drawn in litho or referred to the actual gate length as measured in a process cross section.
It didn't matter so much down to 90-nm but since then the process geometry labels from individual companies have become increasingly arbitrary.
It is noticable that in the memory sector Samsung has started refering to 4X-nm, 3X-nm and 2X-nm for processes in the 40s, 30s and 20s of nanometers.
The node labels are slipping. First 25 nm became 22 nm then 20 nm. Then 16 became 15 then 14 nm. Now 11 nm becomes 10, and probably 9 nm in near future. Then before you know it, a node is skipped (7 becomes 6 nm) and the label becomes meaningless.
My admittedly info in the 450mm delay is simply a matter of who is going to foot the bill for the steppers and mask equipment R&D/fabrication. The 2 or 3 only providers of that equipment have yet to really recover their costs for the currently used max sizes.
Intel and friends are saying "We want this... Design it and let us have prototypes to play with. Development costs? No, you pay for it..."
It's all very strange. I doubt it's because Intel lacks the cash. intel is spending money like it's water to upgrade and build new plants. This is a profit enhancer that will continue to benefit down the road.
Unless something's changed that I don't know about, 10nm is still considered to be iffy, while 450 wafers are not. Yet, they seem to be certain about 10nm.
10nm seems to be a stretch. Intel has been pushing for 450mm wafers for years now, but they ended up wasting money that could have funded the effort due to some poor management decisions that resulted in Intel having to pay out large sums of cash to AMD and nVidia. There is no need to manipulate the market when you have the technology and talent that Intel has had now for multiple decades. The purchase of McAfee, while benign, also seems a bit questionable. I think Intel could have picked a better software company to buy. Software may be a good long term growth opportunity for Intel. But I think buying a linux provider on the cheap would offer Intel more opportunity to expand since linux can be used for multiple platforms, from servers down to handheld devices.
I admit to being a bit confused by this. Larger wafers provide the ability to get a higher yield for various reasons. Larger process technology needs all the help it can get, as there is wasted space due to the large chip size.
Smaller process technology allows more chips per wafer, and less lost area due to smaller chip size. At least, that's how I understand this. So why wait until the 10nm node? It would seem to need this even more now.
Just read ASMLs reveal for first 13.5-nm wavelength EUV lithography tool which would allow productions above 14nm. Interestingly rival Nikons idea is going far beyond, to 6.7nm which converges reportage with Mr. Hobbs. I am kind of confused here, in order to have 450mm wafers which wavelength is going to be used? And perhaps intel will have Nikon as 450mm tool provider?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.