Poor endurance is just one aspect of newer NAND devices that is problemmatic. The other is increasing latency because of the much slower multi-level cells and the the increasing time neeeded for error correction before any of the retrieved data can be used. Cell latency used to be of the order of 20-30uS and 1-bit error correction added almost nothing to that. Now cell latency is 80uS or more and typical NAND controllers add far more.
Our application, which demands low random access latency, used to be practical with NAND but with present trends, may become impractical before we can deliver a product. Does the MSP controller help the latency issue?
You are correct about wear leveling and error correction codes. This product has something else, which we call Memory Signal Processing. It is about applying signal processing methods to the analog voltage levels inside the memory array.
Wear leveling and FEC are nothing new in SD cards, thumb drives and SSDs. Otherwise, the FAT table (written every time you write to a file) wouldn't last long. A flash manager needs to remember sectors that go bad, provide wear leveling, and do forward error correction among other things. A press release wouldn't necessarily say "Ours is better than Theirs because...".
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.