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resistion
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re: Analysis: Litho world needs a shrink
resistion   3/22/2011 8:27:11 AM
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Your stacking example uses logic, but for cost-conscious memory, shouldn't there be concern?

resistion
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re: Analysis: Litho world needs a shrink
resistion   3/22/2011 8:27:11 AM
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Your stacking example uses logic, but for cost-conscious memory, shouldn't there be concern?

docdivakar
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re: Analysis: Litho world needs a shrink
docdivakar   3/21/2011 10:08:55 PM
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While alternatives to lithography challenges is one value prop for 3D, there is also the issue of package connectivity that will force one to adopt stacking chips. The intra-processor communication (IPC) and/or inter chip to chip communication pipelines at higher data rates (40/100Gig) using differential signaling is already congesting the server / switch mother boards. 3D will be a good answer as long as thermal and power management issues are addressed. Dr. MP Divakar

docdivakar
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re: Analysis: Litho world needs a shrink
docdivakar   3/21/2011 10:08:55 PM
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While alternatives to lithography challenges is one value prop for 3D, there is also the issue of package connectivity that will force one to adopt stacking chips. The intra-processor communication (IPC) and/or inter chip to chip communication pipelines at higher data rates (40/100Gig) using differential signaling is already congesting the server / switch mother boards. 3D will be a good answer as long as thermal and power management issues are addressed. Dr. MP Divakar

resistion
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re: Analysis: Litho world needs a shrink
resistion   3/15/2011 9:46:46 AM
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Thanks for the info and references!

resistion
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re: Analysis: Litho world needs a shrink
resistion   3/15/2011 9:46:46 AM
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Thanks for the info and references!

bec0
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re: Analysis: Litho world needs a shrink
bec0   3/15/2011 3:47:21 AM
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Good question resistion. With it's rich vertical connectivity (vertical interconnect density ~ horizontal interconnect density) and shorter wires, we can remove many of the repeater buffers and as well as make smaller drivers between subcircuits. A logic chip would be 2 layers of 25% the size (50mm2 2D becomes 2x12mm2 in m3D). See one calculation at http://www.monolithic3d.com/why-monolithic-3d.html . Another ref is L. Zhou, et al., “Implementing a 2-Gbs 1024-bit ˝-rate low-density parity-check code decoder in three-dimensional integrated circuits”, Proc. ICCD, 2007. It about one node of scaling.

bec0
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re: Analysis: Litho world needs a shrink
bec0   3/15/2011 3:47:21 AM
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Good question resistion. With it's rich vertical connectivity (vertical interconnect density ~ horizontal interconnect density) and shorter wires, we can remove many of the repeater buffers and as well as make smaller drivers between subcircuits. A logic chip would be 2 layers of 25% the size (50mm2 2D becomes 2x12mm2 in m3D). See one calculation at http://www.monolithic3d.com/why-monolithic-3d.html . Another ref is L. Zhou, et al., “Implementing a 2-Gbs 1024-bit ˝-rate low-density parity-check code decoder in three-dimensional integrated circuits”, Proc. ICCD, 2007. It about one node of scaling.

resistion
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re: Analysis: Litho world needs a shrink
resistion   3/15/2011 3:00:48 AM
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3D is probably one of the better options, but is it actually cheaper? It is still cost-additive per layer/plane, isnt' it?

resistion
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re: Analysis: Litho world needs a shrink
resistion   3/15/2011 3:00:48 AM
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3D is probably one of the better options, but is it actually cheaper? It is still cost-additive per layer/plane, isnt' it?

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