Max - since you actually pointed out that you don't consider Cypress PSoC in either category - where does it fit in your view? With over 1 billion PSoC devices shipped in the last 10 years there is certainly a category for them - or do you see them in a category by themselves?
Both Xilinx and Altera have made millions if not billions off customers who were "prototyping" in an FPGA and never got around to doing the ASIC. Lots of reasons for this - FPGA price reductions and evolving standards being just two of them.
It could also be argued that an FPGA by it very nature is a "Master SoC".
Nice article. I take the design start information for the trends they represent and not the actual numbers. Even if the numbers were off by a significant percentage, the trends say that more design teams are starting projects with FPGAs.
The big 2 FPGA vendors have a lot to do with this. If you look at the capacity, performance, power profile of the previous two FPGA technology nodes and then look at the same for the 28nm devices, we have seen a doubling in capacity for raw luts AND many hard IP components/memory added to the technology making the increase in design technology resources for new devices more than doubling with each node.
The result of this exponential increase in FPGA/Design technology resources in new FPGAs is that they take sockets that would otherwise go to ASICs or ASSPs. Xilinx has an example on their web site of a video camera design with the new Zynq device that reduces the size power while increasing performance of the camera. This design is an example of just another socket the FPGAs will be taking.
Of course, there will always be ASICs and ASSPs because there are applications (like cell phones) that always want to do more and push the bleeding edge of technology, and those designs require many more engineers to implement them, so the high-end EDA industry is not in jeopardy, but the richness of new FPGAs is where the growth is.
As FPGAs take share of the low end ASIC/ASSP market, ASIC class tools that are "FPGA tuned" are required. FPGA flow and technology is very different than ASICs. Ask any ASIC guy how his last lab bring-up of his first FPGA went. :) Our company (GateRocket) focuses on that (pardon the commercial).
Be well and please keep the great content coming!
Dave Orecchio, CEO GateRocket
Wonderful article Max!, so many interesting points.
Like many guys i also continuously wondered for years, when you see the marketing tactics of FPGA vendors, it seems whole planet is/eventually going FPGAs... However when comes to ground statistics from revenue stand point (@FrankEory also mentioned similar thing), things are strange!. Comparing Design starts/classifying design starts is indeed interesting to know but very hard to get real data.
The revenue of industry, companies is usually always circulating in community. I thought to investigate for my curiosity indirectly to see How much FPGAs/PLD market actually represent of TAM and how it has evolved over years. Fortunately i found a Graph from Gartner (can be found at : http://www.eetimes.com/electronics-blogs/programmable-logic-designline-blog/4033356/A-dissenting-opinion-on-the-programmable-imperative-) showing PLD market evolution over last decade. It is really intersting, although positive but surely the astronimical markiting hype of FPGA vendors is clearly visible (Where is the money?? :)).
I guess FPGA vendors (BIG2) are really pushing now new devices Zynq... to increase their market beyond tradition. THe design starts comparison to ASIC/ASSPs becomes faded for FPGAs when comes production volume.
As Max has mentioned several interesting and tricky stuff, for me the final design win/actual production (FPGA as product) is more important than design starts wins for FPGAs to move on with their growth :)
"Design start" is a nebulous, perhaps almost meaningless, term used by sales people and analysts to try to predict future sales. Just about any number a person comes up with can be justified, but as you pointed out, only a fraction of that number will actually make it to production.
Trying to separate FPGA design starts from those of ASICs or ASSPs seems like a fruitless exercise.
Production volumes and revenues for each type of chip is of course what counts. Perhaps historical data on production of each type of chip -- over the last quarter, the last year or whatever -- could provide a basis for judging down the forward-looking design start numbers for each type of chip to more accurately predict future volumes and revenues.
It's interesting that the FPGA design start numbers always seem to be an order of magnitude more than ASIC/ASSP design starts, but in unit production volumes and revenue, the situation is exactly reversed.
A reader who asked to remain anonymous sent me a private email noting that things like "design starts" and "design wins" form a perfect example of “you are what you measure.” In the case of "FPGA design wins," for example, field applications engineers and sales guys and gals are often judged on numbers like design wins. Thus, a customer who gets a design to work is almost certainly going to be counted as a “win”. If that customer changes the package, it may well be counted again. If they subsequently add some more logic and move to the next biggest device, it will be counted again.
Then there is the problem that only a fraction of "design wins" will actually make it all the way into production. Projects get canned for all sorts of reasons. A hidden benefit of an FPGA design is that with no NRE purchase order, it is less visible to senior management. So if an FPGA project is scrapped, there is less financial impact and fewer awkward moments with the boss.
The end result is that you need a ton of designs entering the funnel to get a few out the other end that will make any money…
I have two other scenarios to add to the jumble; how about ‘ASSP’ designs that are shipped in private labeled FPGAs, or FPGA designs that go into production with the intent of being converted to an ASIC later, but never do? As the article points out, there are many ways to skin this cat, which is why I don’t think it’s a question of ‘accurate information’ coming from the various vendors as much as it being a matter of what kind of information is available. As you say, we’re really comparing apples and oranges. I think Rich raises an important point when you consider what’s a ‘start’ vs. a new design based on design reuse. It would be interesting for you to get takes from some of the other research houses such as iSuppli and Gartner.
Great article Max! I too would love to get my hands on some of that research. Seems like this industry is notoriously stingy with information compared to other industries. Very difficult subject, and thanks for bringing it up.
Here are some other thoughts.
1. Quantity of designs or value? Both large and small companies use FPGA. The majority of design starts are from small companies, but the bulk of the revenue is from large companies. Which is more important?
2. How different are ASIC and ASSP devices from each other? ASICs are specific to a single customer, and run in high volumes. In contrast, a large number of companies including fabless vendors produce ASSP devices sold on the open market to cover a vast range of applications. From a technical perspective ASSP and ASICs are very similar.
3. How fast are FPGAs replacing ASIC and ASSP devices? Debate rages about whether - and how fast - FPGAs will replace ASSPs. In some cases FPGAs can replace an ASSP device. For instance, a customer using an FPGA with an external ASSP to provide a PCI interface can save money by updating the design to integrate the PCI into the FPGA. However, there are cases where the ASSP is displaced, rather than replaced. Take the situation where the customer decides to adopt serial communication. He may select an FPGA with in-built transceivers and never even consider using external transceivers. The ASSP vendor is denied the opportunity to bid for the business and the FPGA has eroded the ASSP TAM.
4. Should the question be rephrased “what brings most benefit to people”? Nobody could imagine life without cell phones enabled by ASIC technology. Nor could you countenance a world without high speed internet from ASSP and FPGA devices.
...Or perhaps we should ask what technology enables the highest value of end equipment?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.