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resistion
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re: Momentum builds for 3-D chips
resistion   4/5/2011 10:04:46 PM
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TSV area penalty can be quite significant. 1000 on 0.1 mm pitch is already 10 sq. mm.

d_sekar
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re: Momentum builds for 3-D chips
d_sekar   4/5/2011 5:39:58 AM
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Actually, you can find detailed info for paths to monolithic 3D at this page: http://www.monolithic3d.com/paths-to-monolithic-3d.html. The benefits of monolithic 3D are significant, it can provide benefits equivalent to several generations of conventional scaling (more detailed info at http://www.monolithic3d.com/why-monolithic-3d.html). This is largely due to the small via sizes that allow on-chip interconnect lengths to be reduced. If you have more questions, please e-mail us at info@monolithic3d.com

greenpattern
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re: Momentum builds for 3-D chips
greenpattern   4/5/2011 4:55:41 AM
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3D stacking offers electrical proximity but thermal proximity comes along with it.

resistion
User Rank
CEO
re: Momentum builds for 3-D chips
resistion   4/5/2011 4:50:16 AM
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This is the most feasible scenario, but the irony is the more DRAM is used, the worse the performance/watt of the whole system.

3D Guy
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Manager
re: Momentum builds for 3-D chips
3D Guy   4/5/2011 2:09:40 AM
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Well, you can't expect a company website to have detailed technical info!

krisi
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CEO
re: Momentum builds for 3-D chips
krisi   4/4/2011 11:11:45 PM
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To @selinz, sure, stacking already happens but it is still very small portion of the overall IC shipment...power dissipation is and will be a major concern...maybe we should run some water pipes in between the silicon dice to coll things off...Kris

selinz
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Manager
re: Momentum builds for 3-D chips
selinz   4/4/2011 8:05:21 PM
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We're already seeing stacks in mobile products so to assume that this is all mumbo jumbo is absurd. And in a sense, this is wafer scale integration.... We're not talking about stacking 10 P7's on top of each other.

bkeller137
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Rookie
re: Momentum builds for 3-D chips
bkeller137   4/4/2011 7:55:10 PM
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The most promising use of stacked die seems to be for memory on top of processor/logic chips. This could be to enable a huge cache for a CPU or, in the case of mobile devices where they don't use tens of GB of RAM, it could be all of main memory. Any design formerly considering multi-chip modules might now consider stacked die. Note that DRAM will consume less power and produce less heat if it sends the whole cache line in one cycle using TSVs instead of multiple cycles through off-chip drivers.

dirk.bruere
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Rookie
re: Momentum builds for 3-D chips
dirk.bruere   4/4/2011 7:20:08 PM
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Whatever happened to wafer scale integration? I would have thought it easier than cutting and stacking

greenpattern
User Rank
Rookie
re: Momentum builds for 3-D chips
greenpattern   4/4/2011 4:32:05 AM
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We don't bond servers together in a rack for a very good reason. Expect same for wafers.

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