Actually, you can find detailed info for paths to monolithic 3D at this page: http://www.monolithic3d.com/paths-to-monolithic-3d.html. The benefits of monolithic 3D are significant, it can provide benefits equivalent to several generations of conventional scaling (more detailed info at http://www.monolithic3d.com/why-monolithic-3d.html). This is largely due to the small via sizes that allow on-chip interconnect lengths to be reduced. If you have more questions, please e-mail us at email@example.com
To @selinz, sure, stacking already happens but it is still very small portion of the overall IC shipment...power dissipation is and will be a major concern...maybe we should run some water pipes in between the silicon dice to coll things off...Kris
We're already seeing stacks in mobile products so to assume that this is all mumbo jumbo is absurd. And in a sense, this is wafer scale integration....
We're not talking about stacking 10 P7's on top of each other.
The most promising use of stacked die seems to be for memory on top of processor/logic chips. This could be to enable a huge cache for a CPU or, in the case of mobile devices where they don't use tens of GB of RAM, it could be all of main memory. Any design formerly considering multi-chip modules might now consider stacked die. Note that DRAM will consume less power and produce less heat if it sends the whole cache line in one cycle using TSVs instead of multiple cycles through off-chip drivers.