I'm curious as to why TSMC feels that it will become more and more difficult to attract good engineers over time. If anything, I would think that the industry consolidation and job displacement currently underway is leading to a greater surplus of engineering talent. Or perhaps is TSMC taking the long view and seeing this trend driving fewer engineering students to enter the semiconductor field in the next wave/generation? Interested in any thoughts on the matter.
That's a good point Mark. I recently entered the field myself after completing my Physics Ph.D. in '08. Maybe it was just timing, but 2 different senior engineers that I interviewed with both essentially asked why I wanted to enter a dying industry.
The fab engineer job also can produce a very poor quality of life. In my experience, the really good ones leave for more fulfilling careers with greater upward mobility. Well at least that's what I did, albeit I am still working on process R&D.
We are equipment vendors to do our best to maintain the equipment and improve the process for TSMC.
I think fewer engineers or operators doesn't represent the fewer people working in the fab because it will still need more professional vendors to maintain the complicated tools or improve the process in the fab because new generation machines are more complicated and expensive.
Of course many professional people inside the fab without any contingencies.
At the Symposium TSMC said that over the last 5 years they have boosted the number of process R&D engineers by 3x !!
Perhaps they have finally run out of Chinese speaking Process Engr.s trained in the US and this claim of requiring fewer Engr.s as an argument for going to 450 mm is plain wishful thinking.
Maintaining process uniformity over a larger wafer is never a trivial challenge and transition from 300 to 450 mm too will also require a lot of engineering resources - even if modeling etc. will help a lot more in chamber design etc.
450mm makes sense to go to commoditized products like memory and cheap logic but creates one hell of a problem in wafer handling, especially when there is Wafer to Wafer stacking involved. But then again, TSMC said they are going to expand their packaging & test efforts, may be they are on to something that gives them an edge in this 450mm business overall.
Not sure I understand the reduction in engineers either, but you should get twice the parts per wafer without a shrink due to doubling of area.
If you do a shrink, you might get twice again.
If the number of process steps is about constant, then you expect 4x the parts per operator hour.
Intel and others have estimated a 30%+ in cost per chip. It would appear that much of it comes from reduced human hours per chip.