Looking at silicon would solve the problem. However, when one designs the first chip into a new node careful analysis of the leakage distribution is required. Transistor level data should be well understood so that product designs hit specified targets. Without including these statistical approaches to model and fix vt variation, a full design/tapeout would be needed to correctly measure leakage current. So the solution really is to fix the vt variation problem and to design using the correct statistics.

It is incorrect to use nominal devices to calculate product leakages - one really needs to consider the full statistical distribution of devices. However, if the nominal decreases, so will total power. And if the signma_Vt improves, there will be an additional boost at the product level.

Fig 2 is correct. The product of a Gaussian and an exponential is a shifted Gaussian. Actually, the amount of shift is determined by the product of sigma_vt ^2 and swing^2, so the larger the swing (or poorer the short channel effect) and the larger the sigma_vt, the larger the shift to higher and higher leakage. Additionally, the peak value of the new Gaussian is increased by exp(sigma_vt*swing). So again, as swing degrades and sigma_vt increases, the power dissipated will increase. If the graph plottedwas power vs. leakage (and not Vt), the plot would have been log-normal (aka asymmetric as you suggested).

To keep power dissipation under control, all of these techniques and many more are and will continue to be increasingly employed going forward. However, device variability will limit how much can be achieved. Taking device variability into account is a first step to get the real picture, but we really need to work towards transistors that exhibit much lower variability (sigma Vt). This will be needed to obtain significant power reduction on top of circuit and system tricks/techniques.

Kris, dynamic VDD control during operation is an effective method of controlling both leakage and active power consumption. This method is even more effective when transistor variation is reduced because the tighter VT variation allows greater VDD scaling before circuits become non-functional (SRAMs in particular have poor functionality at low VDD because of transistor variation).

On chip gating is already here to cut power to unused functional units.
Off-chip regulation to regulate voltage(s) to specific cores on a per-core basis is getting more common.
More on-chip regulators tuned to optimise the voltage to specific cores based on testing and immediate clock speed requirements have to be the way forward.
It wouldn't surprise me to see eventually little inductors popping up beside CPUs and other complex chips to support on-chip switched-regulators, but linear is coming first.
More and more 'deep sleep' software transparent power control - you just disable the unit, and it automagically throws the state into a backup RAM optimised for low power use and turns completely off.
Shadow FRAM is also interesting - for the device being able to be truly off, and keep state.

Another crucial issue to consider is the duty cycle of the device and the ratio between leakage current and active productive device power use. A given leakage current is much less significant for a device that is continuously productive than for a device that is only used intermittently but has leakage current all the time.

To @Zavier: I like your "even better than you think", you must be working in marketing ;-)....but seriously can't you just look at the silicon data to make less speculative comparison? Kris

Interesting viewpoint. In the specific case of FD-SOI (which you mention at the end), before even considering the variability aspect, it is known that this technology promises lower nominal circuit-level leakage for same performance spec (by reaching a target performance at lower Vdd and with lower Ioff transistors, owing to excellent electrostatic control of transistors). So if now I take into account variability, with sigma-VT reportedly reduced by 50-60% with FD-SOI at the 22/20nm node, the article tells me I will save an additional 75% or more of leakage power at circuit level, right ? Which would mean, next time I'm talking about benefits of FD-SOI (...that's part of my job) I can say : "Leakage reduction with FD-SOI -- it's even better than you think" ;-). Makes sense ?

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