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krisi
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re: Leakage power Ė itís worse than you think
krisi   5/2/2011 8:11:47 PM
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Lucian, good article...what about a VDD control strategy during IC operation? set low local VDD for those groups of ckts that leak, and use higher VDD for those that don't...would that work? Kris

vincentxia
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re: Leakage power Ė itís worse than you think
vincentxia   5/2/2011 9:43:06 PM
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Fig 2 is questionable, it should be unsymmetric.

PhilRoy1970
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re: Leakage power Ė itís worse than you think
PhilRoy1970   5/3/2011 7:24:15 AM
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Agree. Distribution should be log normal ...

Zavier
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re: Leakage power Ė itís worse than you think
Zavier   5/3/2011 4:59:19 PM
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Interesting viewpoint. In the specific case of FD-SOI (which you mention at the end), before even considering the variability aspect, it is known that this technology promises lower nominal circuit-level leakage for same performance spec (by reaching a target performance at lower Vdd and with lower Ioff transistors, owing to excellent electrostatic control of transistors). So if now I take into account variability, with sigma-VT reportedly reduced by 50-60% with FD-SOI at the 22/20nm node, the article tells me I will save an additional 75% or more of leakage power at circuit level, right ? Which would mean, next time I'm talking about benefits of FD-SOI (...that's part of my job) I can say : "Leakage reduction with FD-SOI -- it's even better than you think" ;-). Makes sense ?

krisi
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re: Leakage power Ė itís worse than you think
krisi   5/3/2011 5:09:40 PM
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To @Zavier: I like your "even better than you think", you must be working in marketing ;-)....but seriously can't you just look at the silicon data to make less speculative comparison? Kris

DrQuine
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re: Leakage power Ė itís worse than you think
DrQuine   5/4/2011 1:05:38 AM
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Another crucial issue to consider is the duty cycle of the device and the ratio between leakage current and active productive device power use. A given leakage current is much less significant for a device that is continuously productive than for a device that is only used intermittently but has leakage current all the time.

krisi
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re: Leakage power Ė itís worse than you think
krisi   5/4/2011 1:08:17 AM
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Yet another consideration is temperature as leakage sources tend to be exponentially dependent on it...Kris

SpeedEvil
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re: Leakage power Ė itís worse than you think
SpeedEvil   5/4/2011 10:45:16 AM
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On chip gating is already here to cut power to unused functional units. Off-chip regulation to regulate voltage(s) to specific cores on a per-core basis is getting more common. More on-chip regulators tuned to optimise the voltage to specific cores based on testing and immediate clock speed requirements have to be the way forward. It wouldn't surprise me to see eventually little inductors popping up beside CPUs and other complex chips to support on-chip switched-regulators, but linear is coming first. More and more 'deep sleep' software transparent power control - you just disable the unit, and it automagically throws the state into a backup RAM optimised for low power use and turns completely off. Shadow FRAM is also interesting - for the device being able to be truly off, and keep state.

lshifren
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re: Leakage power Ė itís worse than you think
lshifren   5/18/2011 2:08:04 AM
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Kris, dynamic VDD control during operation is an effective method of controlling both leakage and active power consumption. This method is even more effective when transistor variation is reduced because the tighter VT variation allows greater VDD scaling before circuits become non-functional (SRAMs in particular have poor functionality at low VDD because of transistor variation).

lshifren
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re: Leakage power Ė itís worse than you think
lshifren   5/18/2011 2:08:43 AM
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To keep power dissipation under control, all of these techniques and many more are and will continue to be increasingly employed going forward. However, device variability will limit how much can be achieved. Taking device variability into account is a first step to get the real picture, but we really need to work towards transistors that exhibit much lower variability (sigma Vt). This will be needed to obtain significant power reduction on top of circuit and system tricks/techniques.

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