Hi, I'm interested in Flash energy consumption to complete a fair comparison between different technologies (particularly in NOR and NAND Flash, SRAM). This parameter is normally disregarded in books and so on. Please could you give any clue on orders of magnitude of the static consumption (specified as current/power leakage) and dynamic consumption during random read operation. Best regards, Leonardo
NAND array architecture is fundamentally more efficient (bits/area) than NOR at a given process node. This array efficiency advantage outweighs NOR's smaller peripheral area as densities increase. From a silicon cost perspective NAND will always be less expensive at the highest densities, NOR will always be less expensive at the lowest densities. So from a cost perspective both NOR and NAND will continue to be viable for the foreseeable future.
From a performance perspective both technologies have characteristics that are essential in different applications. (NOR - low latency reads, NAND - fast program/erase rates)
I think the major flaw in that argument is that NAND and NOR are typically used for very different purposes and there are very few typical user scenarios for both beyond holding boot code/data.
Trying to compare them is like trying to compare a Ford F250 with a Porche.
NAND is prefered for general r/w file system usage - for which NOR is pretty terrible.
NOR is prefered for boot code and data, but many systems are dropping the NOR and using NAND to reduce costs. That slows boot, but is a compromise.
I tried to use a typical usage case scenarios. As tb1 mentions x16 NAND is getting hard to find and commands a significant price premium. Note that even if the NAND transfer time were eliminated altogether the NOR:NAND comparision would be 50:1.
One significant NOR usage change is the continuing proliferation of high density SPI. As a NVM product catagory, NOR revenue is more than adequate to fund next generation process development and new product catagories.
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...