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KarlS
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re: SoC realization: Finally the “Killer App” that will allow EDA to grow again?
KarlS   5/13/2011 8:45:15 PM
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Use of IP in an SoC is analogous to OOP, so much can be taken from OOP software development. The EDA tools today do nothing to assist the designer in the early stages, but rather seem to assume that the design is complete at day one. So synthesis optimization is part of the first compile when the design is not complete so it will throw away anything that is not totally connected then only says "sy6nthesized away these nodes". On the other hand an OOP compiler gives meaningful error messages. Another thing the OOP source editor provides selectable information for classes and methods at entry time. HDL source editors offer absolutely no help. Real chips are made up of and/or/invert, not if/else/case/always. The IP should be defined as a class so it can be compiled/instantiated along with the software in the system design. Then the function should be mapped onto the chip. Since the IP class would have been derived from the hardware design, it would be a matter of instantiating the IP modules.

bigtallsimon
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re: SoC realization: Finally the “Killer App” that will allow EDA to grow again?
bigtallsimon   5/12/2011 1:25:59 PM
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@ahshabazz Uncanny timing - exactly my point but 3 minutes sooner!

bigtallsimon
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re: SoC realization: Finally the “Killer App” that will allow EDA to grow again?
bigtallsimon   5/12/2011 1:23:02 PM
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Food for thought. Your point about risk introduced by having at least two distinct teams (software at one end and silicon implementation at the other) is an important one. I agree that the hard boundaries drawn between the 'hardware' team and the 'software' team make it easy for cracks to open up - cracks which unrecorded architectural requirements or assumptions get lost in. A breed of SoC engineer that understands the big architectural picture, the tools and techniques used at each stage and the methodologies for keeping the implementation in line with the system-level models would be of great value. Until there is a critical mass of such engineers, I wonder if the best tools in the world can be readily adopted...?

ahshabazz
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re: SoC realization: Finally the “Killer App” that will allow EDA to grow again?
ahshabazz   5/12/2011 1:20:45 PM
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I think the problem with turnover in the US markets being so high, where are you going to find someone with the incredible depth and specialization to manage these tools when they come along?

old account Frank Eory
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re: SoC realization: Finally the “Killer App” that will allow EDA to grow again?
old account Frank Eory   5/11/2011 2:37:05 PM
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Excellent article! What you call "SoC Realization" is indeed an area where EDA can and must provide new solutions to bridge that gap between system definition and chip implementation.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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