Tg range is 140-270 deg. C, it can be expanded but
lower Tg glasses are not very technological and higher Tg will probably not be power efficient.
I did not observed crystallization in PAC in calorimetry and long-term storage. Based on calorimeter min heating speed estimate for crystallization energy is above 5 eV.
Semyon, thanks for your reply. I was only referring to Figure 1. I accept that it would not be an issue in other cases where the current does not jump so high after exceeding Vth.
I couldn't get to attend MRS so I couldn't get to ask you other questions, such as the Tg range and also the crystallization temperature range.
I agree that threshold voltage Vth drift is possible in switching memory (SM). There are few methods to deal with drift in phase-change memory (PCM) on the active alloy, cell structure, programming pulses and array periphery levels, some of these solutions are applicable to SM. I think one of the most attractive is opportunity to use SM as DRAM with long refreshment times (about 1000 sec) there drift would not be so important.
I disagree with your assumption about destructive read. I was able indeed read low Vth few times without destruction but more studies are needed to claim fully non-destructive read, investigate drift, recovery, temperature coefficients for Vth, etc…..
The PAC films fabrication is not more difficult than fabrication of films for PCM or for threshold switches for nano-devices that have been done by Intel, Samsung and other companies.
Thank you for the review that really extends my MRS presentation.
Let me clarify some points:.
PCM as well as some of types of RRAM have low efficiency (only few percents) because of huge entropy penalties related with operation between ordered and disordered states, while switching memory SM supposes to be more total energy efficient and operates at lower currents.
Ge-Si-As-Te glass was used by Stanford Ovshinsky in stable threshold switches but to best of my knowledge it is NOT polyamorphic.
Although initial current filamentation occurs in SM devices they are NOT necessary should have pore structure, actually I used devices with structure similar to a planar capacitor. I not sure that PAC material must be deposited in the low threshold voltage state for nano-size SM devices but no studies have been performed. Initial values of threshold voltage were masked by imperfections of technology used to produce micro-size devices.
I observed a threshold voltage range of the factor slightly above2 only.
Because no detailed studies of PAC were conducted I do not have data about threshold voltage temperature coefficients.
When I made PCM presentation on behalf of Intel Corporation, managers always asked to use arbitrary units and mirror some relations to protect the company proprietary information and IP, so I learned the lesson and applied it to this MRS presentation.
Volatile Memory: I think I commented in my conclusion on the use of arbitrary units as a problem. Rather than personal attacks I think the first order of business must be for an independent third party to try and reproduce the results reported by Savransky.
Resiston: I agree threshold voltage drift, or post switching recovery, will be an important consideration for PAC based SMs.
If the post switching recovery in threshold switches is the same as in PCM memory devices after reset, then that may be an important clue to the conditions, especially temperature, that exist in the conducting filament of a threshold switch. Be it PAC based or any other type for that matter.