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docdivakar
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re: IMEC, Atrenta to show 3-D design flow at DAC
docdivakar   6/1/2011 6:52:41 PM
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Some EDA startups (who shall remain nameless!) went bust chasing the 3D pathfinding mirage. 3D stacked chip design using TSV's is a system-level challenge. By "system" I mean a complex system of interaction between electrical, mechanical, electromechanical, thermal and thermo-mechanical systems that need to be addressed in the design stage. Overlooking this at the design stage will only lead to costly & time-consuming iterations with prototyping. Of the big three EDA, I believe Mentor is in the best position to address 3D design challenges with the suite of tools it currently has. It will need some missing pieces (like mechanical simulation) to complete the picture. It might as well pick up the assets of some defunct 3D pathfinding companies in the process! Note that Atrenta is not the only one to offer 3D pathfinding, there is R3Logic... Dr. MP Divakar

Warren3
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re: IMEC, Atrenta to show 3-D design flow at DAC
Warren3   5/25/2011 3:47:45 AM
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Yeah, well regarding Mentor, I am thinking Icahn wouldn't think that's such a great idea.

eewiz
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re: IMEC, Atrenta to show 3-D design flow at DAC
eewiz   5/24/2011 12:52:27 PM
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I am really curious why the big guys SNPS/CDNS/MENT didnt acquire Atrenta yet, which is the normal practice in EDA industry! But Atrenta on their part seems not waiting for an acquisition and is making good progress and moving into new domains like 3D design from their traditional RTL analysis tools. Good luck guys.



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