I agree with most of the comments here that this is reflection of the confidence that the company has. Just wondering if this will inspire other companies to come-up with such innovative marketing tactics ?
Every year, auto industry is pumping out of car with a little bit of change from the last year, because they know a customer does not want to buy the 1 year old car with the same price. For a very new car, automaker prepares for many years from a part to assembly line.
A bit different from ASIC industry. ASIC/FPGA/System industry is usually run 6 month or 1 year to compete a new design. As tools and expertise are getting mature, a design phase may become shorter. More over, some of design cycle, particularly in a back-end cycles are almost one push-button style.
Why ASIC design process is delayed sometime is due to a complexity of verification. From what I read other engineers’ article and my experience, there is a bottleneck in verification process. The functional count multiplied by a clock speed is almost impossible to meet a time line. That is why any IP coming up, because it is not my bug, if IP works incorrectly.
I don’t want to argue with Sherwani’s sales pitch. I have to say this is very unrealistic sales talk to a hand-on verification engineer, while it is very attractive offer to Director or CFO level. If you get your money back for a slip of project schedule, it is the one I could bet my money on, regardless who they did it.
Truly a great offering from Open-Silicon, for the first time someone in the silicon asic industry has spoken like words, this also shows the confidence in his field when they give this kind of commitment.
A Book For All Reasons Bernard Cole1 Comment Robert Oshana's recent book "Software Engineering for Embedded Systems (Newnes/Elsevier)," written and edited with Mark Kraeling, is a 'book for all reasons.' At almost 1,200 pages, it ...