Regarding the gray code counter, I found it easiest to use a "toggle" flip flop. The next state equations for an n-bit counter were:
ns(i) := (not cs(0)) and (not cs(1)) and ... (not cs(i-2)) and cs(i-1) and (not cs(i) xor cs(i+1) xor ... cs(n-1))
I believe that the gray code counter will always be larger (binary counter toggle enable is simply an AND of all of the lower bits), use more power and be more difficult to debug. We always use binary counters and convert when we need. BTW: make sure your converted signals are registered if they cross any clock domains, otherwise you loose the benefit of gray code.
Dave Simpson

It may be easier for you to implement Gray counters with T-FF but for fully optimized equations that would not be the case. A good deal of it depends upon the native FF's available (T-FF's are usually permutations of native D or JK). From a logic point of view T's are easy, you write equations for when to change so MSB's are easy and narrow equations while LSB's are complex wide equations. Generally speaking JK's work best for logic reduction because they can essentially function as both D and T with many don't care states. As for power, there are two components, static power is process controlled while dynamic power is a linear function of toggles. Since a full sequence Gray counter asymptotically approaches 2 very quickly it's reasonable to say that they take half the power of a binary counter. For a full sequence Gray counter of n bits there are 2^n toggles while for a binary counter there are (2^(n+1))-2. Or to list binary power cost relative to Gray for n bits 2 through 8: 1.500, 1.750, 1.875, 1.938, 1.969, 1.984, 1.992
respectively.

Hi Clive for yours interesting posts. I hope it would be in a better position to help. I am a final year engineering student and I am to design a sequential circuit which converts BCD to Gray code. Hope you will be able to help.

Thanx Max. I know the code but iam a bit stuck on how to derive the state map for the conversion which i would then use to design the sequeantial circuit.

@BSc Student: i am a bit stuck on how to derive the state map for the conversion which i would then use to design the sequeantial circuit.

I think there are two things here. let's say you have four registers that are used to hole your BCD count. Let's call them b3, b2, b1, and b0. So the first thing you need is a block of combinatorial logic in the feedback path to generate the next BCD value in the count sequence.

That is, you take the outputs from b3, b2, b1, and b0, feed them into your block of logic, and use the outputs from this logic to drive the inputs to your registers, so every time you get a clock pulse the BCD counter counts.

The next thing you need is another block of combinatorial logic that takes the outputs from the b3, b2, b1, and b0 registers and generates your 4-bit Gray code -- let's call these bits g3, g2, g1, and g0.

Take a look at my table -- let's start with g0. The only times this is a 1 corresponds to the BCD states of 1, 2, 7, and 8 (0001, 0010, 0111, and 1000). So we can say:

We would do the same thing for the other three Gray code bits (and we'd use the same technique to generate the next count value for the BCD feedback path).

Then use standard logic minimization techniques (like Karnaugh maps) to make the logic as small as possible.

I hope this helps. Let me know how you get on. Happy Monday! :-)

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