This would be a great breakthrough for the semiconductor industry, both for low power mobile type of applications and for large scale chip designs (lower heat, lower power, better performance). I really want to cheer for the start-up that roars!
I agree they have a chance Nic but looking at the patent application is not entirely clear how one controls exactly position of the dopants which is the key to their low power claims...I am actually amazed that a few people can still get together and challenge well established transistor manufacturing concepts that billion dollar corporation work on with thousands of people on board...cheering for a small guy then, go SuVolta go! Kris
Fujitsu collaboration with SuVolta on this development making the technology available at 65nm process node is an assured step in the commercialization of the technology. And the company's executive slate has impressive players. So overall, I would give the technology a chance to prove itself but I would caution inflated claims to "halfing" power of ICs. What is achievable at the device level may not necessarily translate linearly at the integrated circuit level for acceptable volume production yields.
@iniewski: BTW, a sentence or two of your views here may encourage others to come to you for more in-depth consulting and analysis. Please invite Ashok to chime in...and a question, what kind of process was the JFET based on originally?
Kris, the slides Ashok presented at the conference you mentioned are on JFET stuff. Since then, SuVolta abandoned that approach. The news released today is on bulk CMOS based PowerShrink technology.
Please visit the company website to learn more about this groundbreaking technology...Sang-Soo
Blog Doing Math in FPGAs Tom Burke 15 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...