As far as EDA market is concerned, until there is an integrated flow there won't be a large market for 3D tools. The existing tools will be brute-forced to get by!.
I would argue the 2.5D using Si interposers will lead the market for a while, till TSV-enabled multiple stacks of substrates become commonplace. The drivers for these are several:
1. There is simply not enough space to connect chip packages with a large number of I/O's to the board -the design rules in board layout are limiting, most at 3mil width/spacing. So multiple dice have to co-habit the same substrate in a BGA package. This chip-to-chip driver interconnecting will drive a number of communication IC products for a foreseeable future. This is where the Xilinx's, Altera's will put their effort as you also note.
2. Diminishing latency budget in chip-to-chip communication: examples abound in 40G/100G backplane market, another driver for integrating multiple substrates of IC's that interconnect with each other and are challenged by the prop delays by having to go thru a long, challenging paths. Si interposers provide the most optimum way to interconnect between chips.
3. Integration of passives, including planar magnetics: inductors and capacitors for bypassing / decoupling, power management functions, etc., are easier to to implement with Si interposers.
Dr. MP Divakar
3-D integration, TSVs and stacked die are a huge new area of opportunity for EDA. As these become more common, we designers need EDA solutions to help us ensure 1st pass success with system-in-package (SIP) solutions. The mechanical engineering issues (heat transfer, etc.) are right up there with the traditional electrical issues (timing, signal integrity) that tools need to attack.
Not every IC package will contain a single 28 nm or 32 nm die -- this is quite clear from the economics. But those multi-die packages that for some applications are the most cost-effective solution need a lot more EDA support that exists today.