I'm not privy to their financials, but these guys are in business to make money, so imagine it must cost-effective :).
I would guess the additional complexity and area required for this logic is currently being offset by the die shrinks (i.e. revenue per wafer is still higher). I question whether that can remain true for very long, though. The die shrinks cause more errors, forcing more robust ECC techniques, then the implementation of those techniques requires more die area,power, etc. Seems like a little bit downward spiral to me.
"Is there any model avaliable to simulate ECC in our own flash controller? Thanks in advance. "
This is something that should probably be investigated with the memory vendors (Micron, Samsung, etc.). I'm quite sure they have this, but I don't know if they would share it.
Very interesting and informatic article.
1. In an "Errors and error correction" section there might be a typing mistake which is "the ECC requirements are 4 bits per 512 bytes". It should be "4 bytes per 512 bytes".
2. Is there any model avaliable to simulate ECC in our own flash controller? Thanks in advance.
Very interesting article. In general it is very difficult to implement logic on a memory process, this explains the demise of "embedded memory". Is it really cost-effective to implement ECC on the die of a NAND chip?
Daniel and Agarwal presented this paper at ESC Silicon Valley this spring, and I asked them to put together a version for us on the designline. I think they did an outstanding job laying out the issues facing NVM technologies. Please add your comments or questions for the authors below.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.