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JanineLove
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re: Software and hardware challenges due to the dynamic raw NAND market
JanineLove   6/12/2011 11:49:51 PM
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Daniel and Agarwal presented this paper at ESC Silicon Valley this spring, and I asked them to put together a version for us on the designline. I think they did an outstanding job laying out the issues facing NVM technologies. Please add your comments or questions for the authors below.

Sudarshan NS
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re: Software and hardware challenges due to the dynamic raw NAND market
Sudarshan NS   6/13/2011 7:46:11 AM
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Good one

joshxdr
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re: Software and hardware challenges due to the dynamic raw NAND market
joshxdr   6/13/2011 7:23:00 PM
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Very interesting article. In general it is very difficult to implement logic on a memory process, this explains the demise of "embedded memory". Is it really cost-effective to implement ECC on the die of a NAND chip?

IM105
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re: Software and hardware challenges due to the dynamic raw NAND market
IM105   6/14/2011 12:18:36 PM
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Very interesting and informatic article. 1. In an "Errors and error correction" section there might be a typing mistake which is "the ECC requirements are 4 bits per 512 bytes". It should be "4 bytes per 512 bytes". 2. Is there any model avaliable to simulate ECC in our own flash controller? Thanks in advance.

IM105
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re: Software and hardware challenges due to the dynamic raw NAND market
IM105   6/14/2011 12:47:52 PM
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I am sorry for my previous comment. I was wrong...it is not typing mistake. Please ignore the point(1) in my previous comment.

djallred
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re: Software and hardware challenges due to the dynamic raw NAND market
djallred   6/14/2011 2:43:27 PM
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"Is there any model avaliable to simulate ECC in our own flash controller? Thanks in advance. " This is something that should probably be investigated with the memory vendors (Micron, Samsung, etc.). I'm quite sure they have this, but I don't know if they would share it.

djallred
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re: Software and hardware challenges due to the dynamic raw NAND market
djallred   6/14/2011 2:48:43 PM
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I'm not privy to their financials, but these guys are in business to make money, so imagine it must cost-effective :). I would guess the additional complexity and area required for this logic is currently being offset by the die shrinks (i.e. revenue per wafer is still higher). I question whether that can remain true for very long, though. The die shrinks cause more errors, forcing more robust ECC techniques, then the implementation of those techniques requires more die area,power, etc. Seems like a little bit downward spiral to me.



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