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bhhlophe
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re: Japan takes Sparc to 8 Petaflops
bhhlophe   6/22/2011 6:40:06 PM
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I wonder how many of those systems use FPGAs for algorithm acceleration as Xilinx and Alteration claim massive performance gains. Imagine a supercomputer with Xilinx Virtex-7-2000s that can be cool but also a programming challenge.

J---
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re: Japan takes Sparc to 8 Petaflops
J---   6/21/2011 5:45:17 PM
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We do have cost effective super computing .... it is likely sitting on your desk in front of you! Supercomputing is all time relative. A Cray-1 peaked at 160Mips, 250MFlops.... a small fraction of what the processor and GPU in your laptop and desktop are capable of. So yes, this level of performance will arrive at $100K - $500K, then $5K and maybe even $500 ... it will just take time.

Neo10
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re: Japan takes Sparc to 8 Petaflops
Neo10   6/21/2011 4:46:36 AM
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Quite impressive I would say, that too without using the GPUs for number crunching. That they used a Sparc makes it all the more interesting because of it's legacy architecture. I guess nearly 30% of that power is used by the system itself apart of the cores. But still it is a huge power and could nearly dominate the expenditure for any institution using this level of processing. of course this mega processing would only be deployed in govt R&D and weather stations in drug development by big pharma companies. Though these numbers are pleasing, it would be more valuableto see some really affordable super computing within the budget of a medium sized company, say for ex: $100k-500K

kqalea
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re: Japan takes Sparc to 8 Petaflops
kqalea   6/21/2011 3:42:31 AM
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hmm, I don't think D-wave Get any compiler to use :) beside The D-wave never say they can stable calculate long time 8 Petaflops sound much real to me

selinz
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re: Japan takes Sparc to 8 Petaflops
selinz   6/20/2011 7:56:56 PM
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I'd be curious to see how the users of these system compare. Entertainment, gaming, academic, industrial, etc.

sohonokos
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re: Japan takes Sparc to 8 Petaflops
sohonokos   6/20/2011 4:57:34 PM
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10MW with 68,000 processers?! D-Wave is targeting a couple of Kilowatt pwr with a SINGLE chip processor.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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