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LarryM99
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re: Tilera launches many-core 64-bit processor
LarryM99   6/26/2011 6:48:31 PM
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3D scaling could be important if there is high interdependence between the operations of each CPU, but I maintain that we may have to build new computing models to really take advantage of systems built around CPUs like this. Separate memory for each processor is a good start, since it relieves the bottleneck of access to shared memory. Data centers are a good application for this, because they often work on large numbers of independent transactions. By the way, we may also have to look at the nomenclature. I just realized that this isn't really a Central Processing Unit (CPU). It's more like a Central Processing Pool (CPP?). For that matter, is the 'processor' the chip or each of the sections of it? The same word is used for both in this article. Larry M.

nosubject
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re: Tilera launches many-core 64-bit processor
nosubject   6/24/2011 5:26:53 PM
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It is obvious that Core2Core communication become the bottleneck with the 2D connection for so many cores. Let's go 3D.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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