The tools are based on those used some 25 years ago and the approach has been to just get a bigger hammer and hammer the HDL harder. HDLs are a description language based on the fact that logic can be described by a flow chart. So flow charting was used because programmers could follow the flows and do basic synthesis. Static timing analysis came along at about the same time so that functional(cycle accurate) simulation was used. But the process was modified to use HDL and timing simulation. I think that that was oversold so that it continues today. We just had a long discussion about which language really would be good for design. So far LabVIEW with hierarchical schematics which is based on a data flow programming language has a lot of traction. EDA that does not help the designer tie things together is not a tool -- and we have too many of them floating around. The discussion is in the LinkedIn FPGA Group.