Author should justify his claims with real life examaples. Risk factor are very high and it may need two three or more iterations, adding to the final cost. This is useful only very specific applications.
I have to agree - this is a weak excuse for an "article". Quite obviously, the author has very little real experience with designing high performance linear circuits. Even if the process and asic flow can do the job (and it might) the real differentiators are in the design skill sets and innovation, which are quite different (system, linear, mixed signal, low noise, low distortion, etc) and hard to acquire.
Agree with Bob --- this is (or should be) an embarrassing piece.
At least in the author's defense, the requirement of rather large volumes is advanced. I should hope so. Many of my clients not only want to use off-the-shelf parts, due to small-to-moderate and as well uncertain volumes, but I do my best to assure that parts are available from multiple sources, or that at least substitutions are relatively easy to make.
The idea that I would walk in, say Well here's what I advise: Let all of this go into an ASIC. We'll be waiting months (at least) for first silicon and just have to trust sims of circuits and processes, and that the part comes in at the projected cost, and the company stays in business. But it's going to be worth it because the bill of materials may be a little cheaper.
If there is no other way to achieve some performance requirement, particularly w.r.t. size etc., then maybe an ASIC is plausible. To pursue it to save money seems almost ludicrous.
Sadly, this "article" (a thinly veiled advertisement) represents all that is wrong with trade journalism today. Written by the sales and marketing director for an ASIC company (clearly not objective), it's claims are not backed up with real numbers or case studies and it ignores the many risks, time delays, and hidden costs of designing an IC or ASIC. Indeed, the author relies on the cooked numbers in annual reports (designed to make stock prices look good) to support his overly simplistic assertions about the true cost of making an IC - laughable! I'm sure Bob Pease is rolling in his grave right now. I expect better from EET.
Every function you put into an IC (ASIC or not) adds risk, time, and cost. Most professional designers I know are dedicated to REUSE of proven building blocks to mitigate these challenges. If you are paying too much for your ICs, get a better purchasing agent. Don't reinvent the wheel.
There may be very sound reasons to make an ASIC, but rarely is it to save money. I trust the decades of experience at a solid semiconductor company more than the desparate sales guy at a small ASIC house. And I guess I need to be careful about trusting what I read in EET now. Sad.
All the comments contain very valid points. There are other factors to consider as well, such as (a) reliability of production, (b) repeatability of the specs, (c)reliability of the packaging, (d) design in support, (e) after sales support, and (f) failure analysis and correction. That is aside from the question of whether or not the supplier will/can remain in business. A simple check of Gross Profit Margin as a major decision criteria for the analog ASIC described in the article is VERY risky. These other factors go into the product cost/price as well.
If one can be satisfied on all the points raised, and if a semi-custom collection of analog IP will give one an edge against the competition, and if one can afford the cost and time to tool such a solution, and if one can afford to live with the consequences of being wrong, then give it a shot.
To me, it would be like designing a system using COTS parts from Radio Shack. I don't intend to disparage Radio Shack, but tight specs on the parts they handle just don't exist. Good for general purpose, non-critical applications, but not much else. If you can get that to work, then you could integrate everything on one chip because most likely the actual process technology and performance doesn't matter much.
If the analog ASIC vendor has the same rich IP portfolio as all those analog companies, then it might be possible to integrate all those functions on one die and not suffer any unacceptable performance compromises...maybe.
But how is a single analog company able to precisely duplicate the performance results that took those other companies so many man-years to achieve? The answer is, they probably can't.
Not all op-amps are created equal, and neither are all LDOs -- even when one tries really hard to duplicate a competitor's part.
Have to disagree with the author here. In many cases, analog building-block ICs (op amps, etc) have a uique set of performance specs not easy to capture in an ASIC. That's why a single vendor offer hundreds, even thousuands, of op amps. Each one is tailored to some tradeoff in specs. And when you then try to mix it with other functions, you lose the ability to manage the tradeoffs, you end up with lots of comromises you didn't want.
Believe me,if it was a straightforward as this piece claims, thngs would be very different out there. But the hard reality of analog functions and specs keeps slapping you in the face.
Is it true that all analog components be built with an analog ASIC? Just take the same example in the discussion of using gain controllable precision IA then followed by low power IA and powered them up with a low noise LDO. Some optimized performance of a particular building block is the result of hardwork done by those analog experts in ADI, LTC and NSM etc. I think many people agree some particular op-amps from ADI just can't be replaced by another 8-pin compatible product built by others, even from LTC or TI. If you replace it (op-amp sometimes are thought to be easily replaced as nearly all are pin-compatible), you risk to lose performance. The same applies to the low noise LDO that one can only pick from a particular company. Can a system designer build that functional block with similar performance? In some cases, a Bipolar chip is followed by CMOS chip while the power supply is also built by another fine-tuned bipolar noise noise LDO, even not with design expertise but the performance just comes from silicon processes. Can a single die analog ASIC do all these?