I think that both TriGate and TSV's are 3-D technolgies. Back to the basics of Moore's law - reduction of the area of the transistor and the cells used for creating microelectornics devices will reduce the cost of the manufactring. There are side benfits of potential increase in speed and reduced energy per switching action that can be capture through this effort. Moore's law will end due to laws of physiscs ( how small can switching device get). As part of getting closer to the the physics limit - there is need for more vertical structures to provide the finctionality needed to reduce space. In the previous 15-20 years it was by adding metal layers; Then came incorporation of new materils into the stack that required more processing (layers = vertical additions). Now we are in Tri Gate and TSVs that again - allow to build "High Risers"in different ways ( condos's in the bottom floor, or simply put one strucutre on top of the other). However - we get to the point that the saving will be offset by the ocst of processing and then when Moore's law as we enjoyed it for the last 4 decades, stops- probably a bit before the absolute physical limitaion.
@chipmonk-Yes, of course, we at EE Times are expected to keep up with buzzwords and know the difference between various technologies. We do not upload any articles from the sources that you mention, but we do sometimes write stories based on their reports. When we do that, we reveiew them and make a determination as to their accuracy and credibility. If they don't pass that test, we don't do anything with them. That is what we should have done in the case of the Taitra report--reviewed it and then determined it was inaccurate and thus a non story. But as mentioned above, I made a mistake in this case. My apologies.
Are EE Times Reporters / Editors these days expected to keep up with the latest technology or buzzwords ( e,g. the difference between 3D at the device level as compared to die level ? ). For that matter are articles from various non -technical / suspect sources ( e,g. the Taiwan websites, or for that matter AP, Reuters ) first checked for accuracy before uploading at EE Times ?
The papers presented by TSMC represent a typical format used to assess device functionality and advancement of a new technology node such as 22nm. The format is used by companies as seen from the previous technology nodes such as 45nm and 32/28nm (see old IEDM and VLSI symposium issues). The data are generated on test chip and wafer. The figures from 1-17 as shown in the first TSMC paper are generated from such test chips on several hundreds of data points, but not from product modules because the product wafers are not available yet. To generate such test chip data may take several months to a year and definitely not “one-time results” as you state. I have not seen any university data similar to the figures (1- 17) at 22nm. I don’t think IEDM and VLSI are interested in production data including yield. Beside, company normally dose not publish the product yield data except to its customers. I am sure that companies like Intel, TSMC, IBM and others have already started the test chip design for 14nm to meet Moore’s Law, not for publicity.
I think your definition hinges too much on one-time results for publication. In this case universities beat companies almost all the time. You need sustained manufacturing yield. This is not published, but results in products which may be reverse engineered.
I am glad that you asked the paper numbers because initially I included the paper titles and paper numbers in my post, but deleted because of over the space limit. The title of the first paper is “High Performance 22/20nm FinFET CMOS Devices with Advanced High K/Metal Gate Scheme”, Page # 27.1.1. The second paper title is “A low Operating Power FinFET Transistor Modules Featuring Gate Stack and Strain Engineering for 32/28nm SoC Technology”, Page # 34.1.1. There is no conference digest, but you can obtain IEDM CD by contacting Phyllis Mahoney, E-mail: firstname.lastname@example.org . Intel made a public announcement of its FinFETs and high volume manufacturing around the end of the 4th quarter, 2011. Intel also said it will provide no more technical details at the question and answer session. But that announcement came more than four month after TSMC papers were published. Under these circumstances TSMC reported that TSMC may beat Intel to 3-D chips. Beat here means in my interpretation that TSMC can demonstrate manufacturability of the FinFET chips with reasonable yields, performance and reliability, but not high Volume manufacturing. TSMC may do that. I am also very confident that Intel will meet the high Volume manufacturing schedule this year as reported. If you want to know more about FinFE and its device physics, please read my post in SuVolta’s new transistor option for 20nm – EDN, June 22, 2011. Sang
Dylan, you have adequately explained in the article for the misread -in fact, the entire article is honestly & openly admissive of the error so I don't see why additional apologies / explanations are needed.
I was one of the few skeptics that didn't believe TSMC & Intel were talking about the same 3D when I looked at the title. TSMC is obviously not in the business of developing new incarnations of FETs. Their motivation for monolithic 3D via FinFETs comes from being ready with a process for the same.
The fault lies with too many people using loosely and liberally the term "3D IC" and not recognizing the stark contrasts between various versions of it.
Sorry, we couldn't tag at the Semicon -I was drowning in non-stop ingestion of technical information! Cheers!
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