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resistion
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re: TI touts 3-D packaging technology
resistion   8/5/2011 10:46:45 AM
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To different degrees, other companies have carried out similar disclosures, particularly DRAM makers like Elpida, Hynix, Samsung. But the ownership of heterogeneous integration is TBD.

yalanand
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re: TI touts 3-D packaging technology
yalanand   8/5/2011 9:50:34 AM
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This is great news indeed. So in future we can have smaller and more efficient IC's. Just curious to know if only TI is following 3-D packaging tech? What about Intel and other semiconductor giants?

ReneCardenas
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re: TI touts 3-D packaging technology
ReneCardenas   7/29/2011 9:04:07 PM
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Is this marketing shout out to the world of another me too capability from TI?

resistion
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re: TI touts 3-D packaging technology
resistion   7/28/2011 3:53:05 PM
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I kind of agree with Dr. Divakar. This is one of the simpler more established examples of 3D packaging, and doesn't touch on the issues that for example, TSV-based systems might face, such as accumulating thermals, keep-out zones and parasitics.

GREATTerry
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re: TI touts 3-D packaging technology
GREATTerry   7/28/2011 3:18:48 PM
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3D package is a good idea, if the cost of manufacturing won't up much and yield can still maintain good. Power device surely is a good idea, especially the way the MOSFET is placed can't be no more shorter than this! Hope to see more companies jump into this area and produce smaller yet powerful products.

Dave.Dykstra
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re: TI touts 3-D packaging technology
Dave.Dykstra   7/28/2011 5:41:33 AM
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I think the point here is not whether or not the technology is new, but how well it is implemented, manufactured, and shipped in volume. And yes, we should expect to see many more devices in the future using this technology in more complex ways.

docdivakar
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re: TI touts 3-D packaging technology
docdivakar   7/27/2011 8:30:06 PM
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@Dylan: I hate to rain on TI's parade but there is not much new in their "vertical" technology. Back in 2003, I worked on this idea (along with a former colleague at Power One) and extended it to integrate the MOSFET driver in the same package using Carsem's 38Lead MLP Quad Package (8x4mm). The innovation also used Cu-clips to bond with the source digit-like source pads. The source-to-drain stacking between high side and low side MOSFETs can be done with yesterday's technology, not needing any TSV's! I understand IR and other power electronics players were also working on similar concepts. MP Divakar

_hm
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re: TI touts 3-D packaging technology
_hm   7/27/2011 8:21:28 PM
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This is very good news. With advent of this 3D packaging, TI can introduce many novel features in their product and make SoC very effective. We will see many more product with more complex 3D packaging technology.

goafrit
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re: TI touts 3-D packaging technology
goafrit   7/27/2011 7:46:12 PM
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The number does not tell the whole picture. Simply, has the market share increased from what it used to be?



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