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James Awad
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re: Changing the status quo in processor design: why synchronous is no longer ‘cool’
James Awad   8/9/2011 5:38:41 PM
Dear DK8PP, Thanks for your feedback. I am of course aware of a lot of the past attempts at building asynchronous processors, which is why I feel asynchronous has gotten a bad reputation. Today there are many companies working to revolutionize the semiconductor space with new products and tools for async. If you take a look at some of Octasic's products, you'll see that we've brought to market 2 generations of DSPs that deliver on the promise of lower power and smaller silicon. So I appreciate your skepticism and would be glad to discuss further with you! James

Code Monkey
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re: Changing the status quo in processor design: why synchronous is no longer ‘cool’
Code Monkey   8/9/2011 4:12:56 PM
Chuck Moore's company, GreenArrays, is producing sea-of-async-computers. The MISC story has a long history, starting at iTV, moving through Intellasys and landing at GreenArrays. Chuck designed his own chip design tools to model his asynchronous chips and make the GDSII. It would be interesting to see a history of how his tools evolved from 1980 until now. The chips do indeed achieve very low power, but at the cost of being way outside the mainstream. However, a sea-of-async-computers architecture lends itself to future process nodes where "dark silicon" becomes an issue because of heat generation.

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re: Changing the status quo in processor design: why synchronous is no longer ‘cool’
DK8PP/M   8/9/2011 8:01:56 AM
Well, nice idea, but real results were not so promising. In the 1990s, there was the AMULET group in the Department of Computer Science at the University of Manchester, who developed an asynchronous version of the ARM6, the AMULET1. It used 75% more transistors than the ARM6, achieved about 50% less performance and consumed about the same power. In today's technologies, we have rather high static currents, which means the number of transistors contributes more to power consumption than the toggle rate. Nice idea, worth to be followed-up, but I remain sceptical.

As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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