What I do not see from Fig.1is that at what drain voltages (Vd) the three Id/Vg curves are taken. Assuming that the upper Tri-gate blue curve and lower blue curve are taken at Vd = 1V and Vd = 50 mV, respectively, the DIBL is roughly estimated to be ~110 mV/V and the subthreshold swing (SS) is ~85 mV/decade. For FDTri-gate transistors DIBL, SS and Vt change are expected smaller. The Vt seen here is induced by large DIBL meaning the build-in source barrier is lowered by the drain voltage, resulting in lower Vt and high leakage current. Notice that ~ 0.2mA/um difference between the saturation current (Idsat) as shown by upper blue curve compared with the Idlinear shown by lower blue curve at Vd = 1V for Tri-gate are unusually small. Intel shows 32nm planar Idlinear as indicated by black curve is virtually the same as the Tri-gate Idlinear at Vd = 1V, but dose not show the corresponding Idsat for 32nm planar transistor in Fig.1. However, based on Fig. 3 of Intelís published IEDM 2008-p943, the 32nm planar Idsat at Vd = 1V is 1.55mA/um that is significantly larger than the Idsat of 1.0mA/um for FDtri-gate transistor. Similarly, TSMC 22nm FinFET built in bulk Si substrate published in IEDM10-p600 shows Idsat equal to 1.2mA/um at Vd = 1V which is significantly smaller than Intelís planar 32nm Idsat of 1.55mA/um.Therefore, both Intel FDTri-gate and TSMC FinFET at 22nm show the same transistor performance degradation significantly worse than Intelís planar 32nm, and may need additional fins added in order to boost the transistor performance.
I expect the planar 22/20nm will show significantly higher transistor performance, but higher DIBL and sub-threshold leakage compared to Tri-gate and FinFET. Intel should publish its FDTri-gate device data as done for its planar 32nm to avoid the guess work
Actually it's all very simple: Intel's problem is a that it is stuck in its own paradigma. They have grown 40years+ in the paradigm that x86 is the best architecture and that the IT world belongs to x86. Intel firmly believes this will never ever change, and behaves accordingly. But, in the IT ecosystem appeared a new beast called ARM, with new characteristics, two of the key ones being power efficiency and large licensing base. Now this new beast is starting to challenge the x86 lion, little by little depriving the lion from its "gazelle meat". Would Intel accept that x86 is a thing of the pas and start working on ARM solutions? Otellini would tell you beating his chest with his fist: Never! And that's company ego. And the bigger the ego, the harder the fall...
I wish Windows 8 for ARM had an x86 emulator in order to be able to run all the x86 legacy programs...(today Window 8 for ARM does not support backward compatibility with x86) but it seems more likely that in a couple of years most typically needed programs will have android/iOS versions of them and windows will progressively sink together with Intel. Welcome to the GoogApplarm era!
Very good blog Deepak. I think it would help to split the criteria into quantitative and qualitative ones. The former can be used to make straightforward analytical techniques as you did with power consumption. The latter are more subjective in nature. I personally cannot dismiss the ~28% power advantage of Intel's trigate technology. On the other hand, the 20-50% cost advantage of ARM is also a major advantage. The real advantage however will not come from bare technology alone but from a clear advantage in the final product. The question is then: what are the key comparative advantages when it comes to products, be it in the server or mobile arena? Are there any thresholds in terms of product cost, battery life/power etc. which would make a product a success of a failure? We should then work backwards from these to see what are the corresponding thresholds in terms of bare technology.
@semi111 : you've nailed it. Intel has a cash cow in their process technology, they're addicted to it. So their single trick is more bovine than equine. Those high margins make them vulnerable to disruption. Something that Andy Grove understood very well, but seems Otellini does not.
I agree with the author that Tri Gate is a major engineering achievement-though the idea has been around many years, but putting it in production still a big deal (BTW it took the industry 15 years to implement HKMG). Intel always leading the industry with their transistor technology like USJ, selective epi S/D, HKMG etc. All these great technical advancement keep Intel's Margin high in their core business the Microprocessor and especially the server market (Some people call Intel one trick pony).
On the other hand ARM has done wonderful by putting a great platform for low power using a plain vanilla process with a great success in the low power applications. Please check how many Ipad were sold with A4 or A5 and not an Intel's chip.
@Jay: I read David Kanter's article just now... it looks like guesswork to me. And he guesses 10-20%, not the 28% number I calculate above. Like I said, I know some people who worked on the tri-gate/finfet project at Intel, and they tell me they aren't aware of a scientific paper on this subject.
@iam_girish: You would choose Vdd and Vt based on your activity profile, with the result that leakage is not more than 30% of the total power... pls. check this classic paper on the subject: http://portal.acm.org/citation.cfm?id=368755 But based on the calculations above, tri-gate alone may not be enough to make up for 50% dynamic power difference and 10x leakage power difference between two chips...
I have heard that Intel processors leakage power contribution is ~10x that of ARM, and active power consumption (switching) is ~50% higher than ARM.
This tri-gate transistor technology seem to reduce only active power. Most of the mobile devices are in active mode only for 10-20% of the time, 80% of the time they are in standby/sleep - limiting leakage is key.
Power gating using high VT devices or back biasing etc.. or better architecture with low leakage/high Vt transistor is key for success in mobile industry.
I saw an estimate of 10-20% in David Kanter's take on Intel's 22nm 3D transistors and assumed there must be literature support for it:
Intel's 22nm Tri-Gate Transistors
"Even taking Intelís estimates conservatively, that suggests a performance/watt advantage of 10-20% for power optimized chips versus a planar 22nm process."
I asked some buddies of mine at Intel if there is public literature quantifying chip power savings of their tri-gate transistor vs. their planar transistor. They said no. My colleagues in the transistor community haven't seen any of these papers either. Would appreciate your sharing these references with me, if they exist.
Reg. ARM RISC vs. Intel CISC, it is a whole new analysis. Will try to write about it on my blog one of these days...
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