Breaking News
Comments
Newest First | Oldest First | Threaded View
SrikanthE
User Rank
Rookie
re: How do I reset my FPGA?
SrikanthE   11/9/2012 4:43:07 AM
NO RATINGS
I would recommend a synchronization circuit(rather than the reset bridge) for synchronizing a control signal that crosses between unrelated clock domains. If your input change is more than one capture clock period of the destination clock apart, use a two FF synchronization circuit which provides meta-stability resolution. The synchronization circuit is a two D-FFs cascaded and clocked by the destination clock. The signal clocked by the source clock is connected to the 'D' input of the first flip flop of the synchronization circuit. Also note that a MAX_DELAY constraint should be placed on the connection between the flip-flops so that they are physically placed close together to reduce the probability of conducting a meta-stable condition. If your clocks are related then to it should be covered by the relative period constraint.

mediterranean
User Rank
Rookie
re: How do I reset my FPGA?
mediterranean   11/7/2012 4:21:16 PM
NO RATINGS
Very interesting article indeed. I am wondering if this way to synchronize a reset signal (to generate a reset which is synchronous with your clock) would only apply to resets or also to any other type of signal. Say you have a certain signal synchronous to the uBlaze clock at 100MHz for example, and you would like to use it to control a block of logic that runs at 180Mhz, could you also use the 2 flip-flops and use it as async reset (or preset) to generate a sync signal? If not, what is the best way to do this? Thanks

nic2
User Rank
Rookie
re: How do I reset my FPGA?
nic2   1/17/2012 3:44:13 AM
NO RATINGS
Larger designs suffer even more with these issues. Using these techniques in larger designs has higher payoff!

nic2
User Rank
Rookie
re: How do I reset my FPGA?
nic2   1/17/2012 3:43:06 AM
NO RATINGS
This is a great article! I used this reset synchronizer design in an article I wrote. It is at http://nicisdigital.wordpress.com/2012/01/16/digital-design-system-resets/ Another issue to consider is the routing resources that synchronous resets consume. There are easy ways to overcome this.

SanthoshReddyA
User Rank
Rookie
re: How do I reset my FPGA?
SanthoshReddyA   12/2/2011 10:35:54 AM
NO RATINGS
Congratulations on what you did, In small projects, this reset seems to be best suited. Is these ideas and methods are applicable to large projects & other FPGA makes?

DrFPGA
User Rank
Blogger
re: How do I reset my FPGA?
DrFPGA   8/23/2011 7:31:22 PM
NO RATINGS
A good companion piece to this one would be 'How do I clock my FPGA?' After that 'How do I initialize my FPGA', 'How do I power my FPGA' and then maybe 'How do I design my FPGA for low noise (decouple, route, etc)'. All very basic but critical issues...

Max The Magnificent
User Rank
Blogger
re: How do I reset my FPGA?
Max The Magnificent   8/10/2011 4:01:00 PM
NO RATINGS
This is a really useful article. If you have a design topic that you would like to write about for me to post here at Programmable Logic Designline, please contact me and let's chat about it (max@CliveMaxfield.com)



EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Tiny Kickstarter MCU Board Provides 'Smart Fusion' for IoT Systems
Max Maxfield
Post a comment
Just a few minutes ago as I pen this words, I received an email from my chum Mike Hibbert, who is a columnist for the computer and electronics hobbyist magazine Everyday Practical ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
20 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
15 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
46 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)