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Max The Magnificent
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re: How do I reset my FPGA?
Max The Magnificent   8/10/2011 4:01:00 PM
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This is a really useful article. If you have a design topic that you would like to write about for me to post here at Programmable Logic Designline, please contact me and let's chat about it (max@CliveMaxfield.com)

DrFPGA
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re: How do I reset my FPGA?
DrFPGA   8/23/2011 7:31:22 PM
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A good companion piece to this one would be 'How do I clock my FPGA?' After that 'How do I initialize my FPGA', 'How do I power my FPGA' and then maybe 'How do I design my FPGA for low noise (decouple, route, etc)'. All very basic but critical issues...

SanthoshReddyA
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re: How do I reset my FPGA?
SanthoshReddyA   12/2/2011 10:35:54 AM
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Congratulations on what you did, In small projects, this reset seems to be best suited. Is these ideas and methods are applicable to large projects & other FPGA makes?

nic2
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re: How do I reset my FPGA?
nic2   1/17/2012 3:43:06 AM
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This is a great article! I used this reset synchronizer design in an article I wrote. It is at http://nicisdigital.wordpress.com/2012/01/16/digital-design-system-resets/ Another issue to consider is the routing resources that synchronous resets consume. There are easy ways to overcome this.

nic2
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re: How do I reset my FPGA?
nic2   1/17/2012 3:44:13 AM
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Larger designs suffer even more with these issues. Using these techniques in larger designs has higher payoff!

mediterranean
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re: How do I reset my FPGA?
mediterranean   11/7/2012 4:21:16 PM
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Very interesting article indeed. I am wondering if this way to synchronize a reset signal (to generate a reset which is synchronous with your clock) would only apply to resets or also to any other type of signal. Say you have a certain signal synchronous to the uBlaze clock at 100MHz for example, and you would like to use it to control a block of logic that runs at 180Mhz, could you also use the 2 flip-flops and use it as async reset (or preset) to generate a sync signal? If not, what is the best way to do this? Thanks

SrikanthE
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re: How do I reset my FPGA?
SrikanthE   11/9/2012 4:43:07 AM
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I would recommend a synchronization circuit(rather than the reset bridge) for synchronizing a control signal that crosses between unrelated clock domains. If your input change is more than one capture clock period of the destination clock apart, use a two FF synchronization circuit which provides meta-stability resolution. The synchronization circuit is a two D-FFs cascaded and clocked by the destination clock. The signal clocked by the source clock is connected to the 'D' input of the first flip flop of the synchronization circuit. Also note that a MAX_DELAY constraint should be placed on the connection between the flip-flops so that they are physically placed close together to reduce the probability of conducting a meta-stable condition. If your clocks are related then to it should be covered by the relative period constraint.



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