@Attoman I agree with you that there is real challenge in process development. I feel leakage will be biggest gating facotr. I am not sure if high-K dielectric will solve all the leakage problems at 14nm.
@greenpattern: I agree... how ever, in the evolving 3D stacked IC ecosystem, even though packaging houses hold the cards, the business model is not yet clear as to who 'owns' the yield issues! So far, 3DIC via stacking has been a niche play for a few companies but its real growth can come from fabless design houses who can productize the technology with applications (of which software is a big part of innovation). When that happens, who do they engage first? Foundries or the packaging houses, or both? The last one may be the obvious choice but my hunch is not many fabs or packaging houses are willing to give a minute of their work day to an ASIC startup or small companies.
Foundries like GloFo, if they want to spur product innovation, can certainly do a lot more by leveraging their partnerships they just announced with Amkor.
Hey Rick, Come On. Where are the tough questions? Did you ask about the yield on 32nm? Did you just take their answer that they are done with 32nm! Why cant you ask the tough questions like an honest journalist would do! EETimes is becoming more of a PR company than a Technical oriented company! What the heck is going on with Llano supply issue? Is it an issue with their process? Whats with Bulldozer delay? Come on.
@Rick Merritt: it was good to meet with you again at GloFlo's conference.
In the afternoon tracks, I sat in the manufacturing track and got some good info on their packaging and MEMS plans. I am not how ever sold on the fab-less model for large volume MEMS which is still an IDM play led by ST & TI.
@greenpattern: you are some what partially correct. The gray-shaded area is like this: if there is backend fab activity (like flipchip, RDL, Si interposers) in a product, then the options are wide open, a fab like GloFlo can get that action though packaging houses can also play. But being upstream in that flow gives fabs an advantage.
Dr. MP Divakar
Blog Doing Math in FPGAs Tom Burke 23 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...