TMSC’s warning about cost/complexity of EUV at 14nm and delays in the 450mm transition supports a growing pool of evidence that the 28/20nm nodes will be in production much longer than historical life cycle. This suggests that device-level innovation will need to continue on the planar transistor platform into the foreseeable future. Foundries and design houses alike will seek to enhance power/performance trade-off and try to maximize product level benefit from 28nm/20nm technologies. A 14nm technology is certainly physically achievable, but its likely going to be limited by cost/economics.
No company can go purely on its own anymore.
At least lithographically, Intel's risk is reduced by memory makers esp. NAND flash like Micron and Toshiba. They validate existing lithography tools can go down to 1X nm. Logic half-pitch is actually a generation behind NAND flash.
As for high-k, some may question if it really is advantageous. Qualcomm for example, skipped on high-k at 28 nm. And Atom power consumption is still considered pretty high. So if tsmc bet all on high-k like Intel, that would have been an instance where it would have been wrong.
The newest development is the finfet or multigate, which Intel showed at 22 nm. But this technology was already available years ago.
Intel should get credit for reducing the risk of transitions like these. But these transitions for Intel are for only one type of product, x86 microprocessors, which hardly applies to memory makers or fabless/foundries.
The message here is that TSMC does not have what it takes to go to 14 nm on its own. Its waiting for Intel to figure it all out and then once again will get the technology free via the equipment suppliers ( as happened with ALD for gate last HKMG ) - albeit 2 years later. What if Intel now decides to do a lot more of the tool development for future nodes in - house and thus crush these bottom - feeding pretenders ?
I would speculate that optical lithography with multiple patterning and all the other process tricks and advanced layout schemes could get us down to about 11 nm. If EUVL is not more capable and cost effective by then we will see the effective end of Moore's law.
I believe that we could indeed see 14 nm design node chips in 2015. I believe that Intel and others see a clear path for multiple patterning using optical lithography at 14 nm. But because this approach is so expensive chip companies are looking for cost reductions elsewhere - such as the economy of scale of switching to 450 mm wafers to help offset the increased expense of lithography. The bigger question is will those companies be able to make any money on those chips?
@RobDinsmore: agree with some points you make above. The industry is still struggling with handling thinned wafers (like 3um, as in what is needed for 3D chip stacking) at 300mm. Handling thin wafers at 450mm will be exponentially harder. Secondly, there aren't many companies left in the test space to provide wafer probing gear (probe cards, test interfaces, etc) so the cost of NRE will be quite high. I think 450mm for 2015 is too optimistic unless the market needs change drastically by then.
Dr. MP Divakar
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.