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ArtB_#1
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re: Update: Nvidia five-core chip ups mobile ante
ArtB_#1   9/21/2011 9:59:16 PM
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One unanswered question is whether a quad core plus a companion core for reducing power consumption will work better or more efficiently than the asynchronous cores developed by Qualcomm.

Athlor
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re: Update: Nvidia five-core chip ups mobile ante
Athlor   9/21/2011 9:52:11 PM
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It sounds amazing, once again I'm surprised by Nvidia and I'm intrigued by the ways one could utilize this 5th companion core.

kmonsen
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re: Update: Nvidia five-core chip ups mobile ante
kmonsen   9/21/2011 8:44:32 PM
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Besides high Vt vs. low(er) Vt, There are other variations of libraries, as well: - 9-track vs. 12-track - long-channel vs. short-channel (The latter makes a big difference in the leakage characteristic, especially how much it goes up at high temperature.)

selinz
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re: Update: Nvidia five-core chip ups mobile ante
selinz   9/21/2011 8:25:43 PM
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There are typically so many unrelated things going on in a typical smartphone that I would think that multiple cores would be easily utilized.

old account Frank Eory
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re: Update: Nvidia five-core chip ups mobile ante
old account Frank Eory   9/21/2011 8:17:00 PM
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Agreed. Rick, you did not need to go out on a limb with "Although it provided no details, Nvidia presumably implements the device as two die in a system-in-package." The companion core could easily have been synthesized with the LP (high Vt) library, and the rest of the chip synthesized with the GP (lower Vt) library and integrated on a single die.

AP81
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re: Update: Nvidia five-core chip ups mobile ante
AP81   9/21/2011 6:46:25 PM
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I wonder If software (OS) can cope up with these many cores. From hardware point of view, you can have as many cores as you want, whether software can take advantage of these cores ? So far, I haven't seen multiple improvements in processing speed by increasing number of cores... comments will be appreciated.

Paul A. Clayton
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re: Update: Nvidia five-core chip ups mobile ante
Paul A. Clayton   9/21/2011 3:42:48 PM
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I also just noticed the statement: "including the time to switch cores within the chip". While 'chip' is sometimes used loosely to refer to an integrated package, it seems likely in this case that it is a single die.

Paul A. Clayton
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re: Update: Nvidia five-core chip ups mobile ante
Paul A. Clayton   9/21/2011 3:36:22 PM
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The white paper indicates that the shared L2 cache latency is the same for the 'Companion' core as for the other cores, so it is very unlikely that it is on a separate chip. Furthermore, even with package-level integration, an additional chip hop (to reach L2 cache, memory controllers, and I/O interfaces) would presumably have a noticeable power penalty. The table entries for Process Technology "Low Power (LP)" (for the Companion core) and "General/Fast (G)" does imply different process, but this might be a simplification for the sake of the whitepaper's target audience.

jeremybirch
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re: Update: Nvidia five-core chip ups mobile ante
jeremybirch   9/21/2011 3:15:37 PM
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You would not need to use two die for this, you can just synthesise against a low power rather than a high performance library. If leakage was the issue then you could use well bias tricks to get around it, or have a double oxide process to have thick oxides for the slow gates - this is a bit but not that rare, but two dies is surely a bad solution?

Robotics Developer
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re: Update: Nvidia five-core chip ups mobile ante
Robotics Developer   9/21/2011 2:57:48 PM
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Interesting idea, I wonder if others will pick up on this as a way to encourage longer battery life and more "instant on" performance?

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