With tri-gate and FinFETs the electrostatics are much better. Intel has several presentations on their web site showing the advantages they claim from tri-gate vs. bulk planar- which are generally accepted/acknowledged throughout the device community. Poke around here and see:
Surprisingly (to me), I heard they will not present performance details at IEDM- I guess we can wait and hope for VLSI.
I understood that Intel is introducing FInFET at 22nm while the rest of the industry will wait for 14nm. WIll there be any advantage in terms of the performance that Intel will gain? The advantage of knowing the problems and getting to the solutions first is clear. Does anyone know the reason behind Intel's move to introduce FInFET at 22nm?
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.