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docdivakar
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re: Price cited as top challenge in 3-D stacks
docdivakar   10/28/2011 6:32:05 PM
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@KB3001: TSV technology of today has ways to go and is still cost-prohibitive as the article says. The keepouts penalties on the real estate is a bit too much for low-cost memory applications. If we approach below 5u dia TSV's in large volume production, there is a play in the market. TSV technology is also needed even in 2.5D incarnations for chip to chip communications that can not be otherwise realized on board with separate components. MP Divakar

dirk.bruere
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re: Price cited as top challenge in 3-D stacks
dirk.bruere   10/6/2011 9:24:37 PM
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30 years ago I remember naively thinking that as more transistors were crammed onto chips, the fewer pins would be needed on the package.

goafrit
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re: Price cited as top challenge in 3-D stacks
goafrit   10/6/2011 5:22:07 PM
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That happens for every new innovation. No surprises there.

chipmonk0
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re: Price cited as top challenge in 3-D stacks
chipmonk0   10/6/2011 10:04:52 AM
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Nothing very original here in that "price will be a roadblock for wide spread adoption of 3D TSV stacks " ! New packaging technologies like TSVs have always had to wait for a killer application to come along and volume to grow before consumer electronics vendors like Qualcomm can afford to use them. Meanwhile niche players like Tezzaron have been making memory modules w/ TSV for a few years already. Reducing the latency for off CPU DRAM ( for Servers etc. ) by TSV provide them with a big enough niche. But the high bandwidth ( wide I/O ) and lower power potential for TSV memory stacks remains very tempting for the handheld segment. It would perhaps take the next Jobs to rise and define the killer application ( movies ? ) for TSVs before current TSV leaders like Elpida or Samsung can really risk HVM. Words of caution. Not only would the TSV vias themselves take up die real estate but they would also require additional keep-out zones for via-induced stress fields. So the adoption of something obvious & grossly mechanical like TSVs might get delayed if elegant electrical alternatives can be worked out at the die & package level.

resistion
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re: Price cited as top challenge in 3-D stacks
resistion   10/6/2011 5:17:41 AM
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I think probably a fairer (and definitely more preferred by TSV folks!) way of assessing cost is to consider TSVs only in the I/O/board domain. Then they will appear as the Moore's law analog of shrinking with better performance, at the interchip level rather than intrachip level.

resistion
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re: Price cited as top challenge in 3-D stacks
resistion   10/6/2011 4:18:48 AM
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"More broadly, TSVs could help the semiconductor industry keep on its historic rate of offering a 30 percent cost reductions in transistors every year. Rising costs of lithography due in part to delays in extreme ultraviolet technology may challenge the industry to maintain that pace without TSVs, Nowak said." I think the two points confused are that EUV itself will impose higher costs and TSVs take up area that can be used for transistors.

KB3001
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re: Price cited as top challenge in 3-D stacks
KB3001   10/6/2011 12:08:40 AM
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Yields will improve with time as fabs develop more robust procedures. This will happen because the case for TSV technology is simply too strong as we reach the limit of tansistor feature sizes.



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