This is getting more hilarious than the PCM/PRAM scam! So Meg Whitman's company and Hynix, two companies that can't get their own houses in order, are going to have a chip in 18 months? If this is a ploy for Mr. Williams to somehow keep his job a few more months, surely it won't work.
What is interesting is that for PCM and now for Memistors both IBM and now HP/Hynix have abandoned the dreaded product road map and replaced it with specific NV memory targets. IBM has 2016 for PCM in its servers and now we have HP/Hynix claiming they will have devices that will challenge Flash in 2013.
This allows the question, what will need to happen as the intermediate steps in order to achieve those particular target dates. In house, chip design, mask sets, development and proving of the fabrication process, full characterization and full reliability testing. Plus all the other steps that allow cost competitive memory product to be put on the market
What will it take to be competitive with Flash? Will there be a continuity of chip bit capacities for HP/Hynix or will they go for the big bang-that now needs to be 1G-bit plus. My view with respect to the 2013 target for HP/Hynix Memistor, is unless they are well advanced with respect to most of the in-house steps mentioned above the target is unlikely to be met and the motive behind making such an announcement now must be questioned.
Unless, in the very near future (early 2012) Samsung, Micron or Hynix announce a performance and price competitive scaled 1G-bit PCM product, I cannot find any way to be optimistic that even the long-range claim of 2016 by IBM for their PCM application will actually be met by a PCM based device.
Yes, a claim of "Whatever the best in flash memory is, we'll be able to double that.", when he has no idea where FLASH will be in 2013, is falling into the old trap of comparing what you have in the labs, with the alternative in volume production.
A message for stockholders perhaps, not customers ?
Somebody is going to make one of these variants work commercially... the basic physics is sound and reproducible. Whether that will be HP/Hynix on their claimed schedule .. I wouldn't bet on that.
My guess is that we'll see it first in really high-end server hardware, or possibly "big iron," for cache. IBM rather aggressively added eDRAM L3 cache to the Power7s ... which I thought was a bit gutsy since they are sold as Hi_Rel. IBM might be the first to roll out memristor cache.
Lee Harrison: Really high-end servers use SRAM and capacitors (and/or batteries). The basic physics was sound for PCM/PRAM as well, initially, until it turned out that the basic physics was actually quite misunderstood and wrong. HP and Hynix have neither the resources nor the management attention to produce a new chip within 18 months. Period. Samsung, who actually may have a better patent portfolio for the memristor, have learned their lesson after the PRAM fiasco. IBM is finished - just look at their millipede storage (those are the same people who are "working" on PCM/PRAM after that disaster).
So, no IBM is not rolling out any memristor cache.
Kudos to HP Labs and Stan for getting to a point where a product is on the--albeit distant--horizon. Clearly there are many pitfalls between now and 2013 they will have to avoid, but this is (literally) promising.
"However, in 2008 researchers from HP published a paper in Nature that tied the hysterical I-V characteristics of two-terminal titanium oxide devices to the memristor prediction of Chua."
It's hysterical, all right.
A little perspective to early semiconductor memory history provides that there needs to be a need from a customer for a new technology. Is there a compelling one for the memristor?
From TI's early days chronicles: "In the early 1970s, a customer approached TI to develop a 1-K MOS memory, but the company elected not to pursue the contract because of insufficient design resources. Memory activities began in earnest when TI second-sourced Intel's 1K-DRAM. Later, TI began a conversion from metal gate to silicon gate designs. In 1972, a decision had to be made to predict the next generation of DRAM, either 2K or 4K. TI started a 4K program, which turned out to be the right choice. The 4-K DRAM became a significant product in the industry.
By 1974, TI had 4K DRAMs (both 18- and 22-pin versions) available."
There was a flurry of news abut memristors maybe 6-9 months ago, then, for the last few months, now news at all. Then a few days ago, there was news from Unity Semiconductor about their memristor device. Now, a few days later, this news from HP/Hynix. I hope it's all true, but it's hard to know. What I don't understand is that Hynix and Toshiba (Samsung?) recently stated http://www.eetimes.com/electronics-news/4217803/Hynix-Toshiba-MRAM that STT-MRAM was the future and didn't even mention memristors. What's going on here?
If HP/Hynix can deliver on this promise it would truly be disruptive to the memory industry as we know it today. But given the sparse details about this technology, I take this announcement as more wishful thinking than a solid plan.
Atleast the statements sound really confident about the schedule. I do not think they have to release the complete roadmap to public now. If they can get it right I hope this will keep HP back on track.
I was surprised HP tried to tag this to the Leon Chua work in 1971 (based on charge and flux) - there is no technical basis for doing that, as HP's design has neither charge nor flux, but perhaps it was a ploy to protect against counter patent claims, and it talks-up share prices ?
Can anyone imagine the old HP placing bluff and bluster, ahead of facts ?
The memristor is a resistive component which conducts current both ways, a fundamental disadvantage vs. semiconductor devices. A crosspoint matrix of memristors is filled with backdoor paths. Some sort of diode function is required for row-column selection. No mention in these press releases of how that is done. Presumably they're just not disclosing their solution to this problem. Time will tell.
I asked Stan Williams about how they coped with bypass paths and whether there is a need for blocking diodes or access transistors (which would hurt the goal of 4F2) and he said they were not required - but would not say more.
I understand there are numerous access methods which get round this problem (pun) but I understand they add to complexity in the peripheral circuitry and sometimes in the matrix itself. So either way you hurt the goal of 4F2.
There are some schemes for dealing with the sneak paths, discussed in the literature.
Without a doubt, when implemented, this class of memory would have to be stacked in multiple layers, resulting in much less than 4F2.
But I think using Pt is an unattractive side of his memristor.
Platinum electrodes sandwiching titanium dioxide was an early manifestation of the RRAM/memristor. I am hearing that research groups have moved on to other contact materials and highly engineered stacks of metal-oxides layers. Clearly using fab friendly materials is one of the many things researchers are shooting for.
What good are memristors and other memory devices when the IT dept at my company will not allow me to send files bigger than 10MBytes through my email.
I think someone needs to invent and implement a "mem-IT" dept so I can send bigger files!
Problem with FRAM is that it can't achieve equal or higher density than Memristors. We can use FRAM right now... through TI or Ramtron or who-ever. FRAM is cool but very expensive... and only available in low densities. 2012 is not the end of the world, it is maybe just the end of Flash? lol.
Go for it HP!! You can do it.
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