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ATUL SRIVASTAVA
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re: Perfecting the 3-D chip
ATUL SRIVASTAVA   10/13/2011 6:32:55 AM
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This will obviously need new generation of EDA tools too . What is the status on that front ?

Rchandta1
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re: Perfecting the 3-D chip
Rchandta1   10/13/2011 12:04:26 AM
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.."volume commercialization of heterogeneous stacks of processor, memory, mixed-signal, networking and I/O chips formed into silicon skyscrapers as high as 100 chips per stack .." - this is very ambitious goal!! Generally sounds reasonable, but very skeptical of the idea of liquid cooling. May fine for special application but definitely not for commercial.

resistion
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re: Perfecting the 3-D chip
resistion   10/12/2011 6:32:45 PM
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One also mustn't lose sight of 3d interconnect taking up more and more area especially with more and more stacked dies.

resistion
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re: Perfecting the 3-D chip
resistion   10/12/2011 6:30:25 PM
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Hope that can remain an option not become a specific requirement. :)

elctrnx_lyf
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re: Perfecting the 3-D chip
elctrnx_lyf   10/12/2011 6:19:52 PM
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will this technology be complete future in the next few years to much higher density processors on a single chip.

JoeData
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re: Perfecting the 3-D chip
JoeData   10/12/2011 5:49:15 PM
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Sounds like a perfect use for industrial diamonds - underfill material!

chipmonk0
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re: Perfecting the 3-D chip
chipmonk0   10/12/2011 5:11:26 PM
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An excellent overview of current 3D status and roadmap except for the glaring omission of Allvia - a small foundry located right here in Si Valley that has pioneered TSV technology at a prototype level for the last 5-6 years and provides smaller customers access to this technology. They also have Si Interposers with integrated capacitors.

Astronut0
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re: Perfecting the 3-D chip
Astronut0   10/12/2011 4:19:51 PM
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hm: You're right! Although 3D itself shouldn't affect lifetime (none of our 3D-ICs from 2004 have failed yet), when more circuitry is added the mean time between failures is likely to become unacceptably small. Continual on-chip testing may be the answer.

_hm
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re: Perfecting the 3-D chip
_hm   10/11/2011 11:04:10 PM
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Long term reliability of these parts is also of concern. There has to be new testing methodology.

resistion
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re: Perfecting the 3-D chip
resistion   10/11/2011 10:48:52 PM
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The serial nature of stacking and the vertical thermal proximity are fundamental concerns.

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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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