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Oscar Law
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re: Perfecting the 3-D chip
Oscar Law   10/18/2011 1:08:43 AM
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I think that there are still few challenges for 3D IC design: - How can we test all IC before they are stacked together? - Most of current 3D IC is limited to memory or sensor only, it takes time to develop complete strategy for stacking real ASIC together - Wafer handling and KGD becomes nightmare for product engineer - How can we handle thermal issues? - 3M approaches may be good solution and we shall see how to apply this for production. However, I don't prefer liquid cooling solution, it is too complicated for implementation - New 3D chip architecture related with TSV placement will solve the problem with lower cost - Is new 3D IC EDA tools required or not? - I prefer hybrid 3D IC design flow, it re-uses most of current ASIC flow with minor modification, it not only reduces the cost but also shortens the design cycle. For example, the multiple die physical verification time can be reduced by 10X or more through minor changes in current flow.

docdivakar
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re: Perfecting the 3-D chip
docdivakar   10/13/2011 11:30:23 PM
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I agree... secondly one must realize that 3D IC design is also a packaging exercise so that needs to be addressed concurrently. Otherwise, there will be costly repititions and try outs of what is manufacturable. MP Divakar

docdivakar
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re: Perfecting the 3-D chip
docdivakar   10/13/2011 11:27:20 PM
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@Colin Johnson: other entities involved in 3D IC standardization is GSA which has been meeting 4 to 6 times a year on this topic, and Si2 Consortium. IBM's work in 3D IC by stacking is nothing new, definitely not a secret. At CANDE 2010 and also at GSA 3D Standards meeting earlier this year, there were presentations by IBM folks so I am not at all surprised. What surprises me is 3M taking on the challenge to develop a thermal interface material with high conductivity for gaps less than 1um. My earlier posting on 3D-related article is here: http://www.eetimes.com/electronics-news/4215464/Si2-to-form-3-D-IC-standards-group?cid=NL_EETimesDaily MP Divakar

Astronut0
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re: Perfecting the 3-D chip
Astronut0   10/13/2011 7:48:58 PM
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collin: 3-D video is a very different thing from 3D-ICs. 3D-IC refers to a way of designing and manufacturing chips; 3-D video is an application. No relation.

Astronut0
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re: Perfecting the 3-D chip
Astronut0   10/13/2011 7:47:04 PM
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ATUL: Micro Magic, Magma, and R3Logic all have 3D-aware EDA tools; but there are still some gaps in the 3D toolset.

Astronut0
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re: Perfecting the 3-D chip
Astronut0   10/13/2011 7:42:02 PM
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resiston: Many of the 3D interconnects won't go through the whole stack, just 1 or 2 layers. Only the signals to the outside world need to emerge at the surface.

chipmonk0
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re: Perfecting the 3-D chip
chipmonk0   10/13/2011 7:28:48 PM
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yes, the TSVs will take up about 15 - 20 % space on a die ( including the bond pads & keep-outs to isolate transistors from stress induced by the TSVs ) but this would be a wash since no large bond pads would be required for wire bonds any more. Because of the short I/O length ( low loss ) and high I/O density possible, TSVs will enable a lot of high - perf / low - power / compact designs.

chipmonk0
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re: Perfecting the 3-D chip
chipmonk0   10/13/2011 7:17:17 PM
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vapor deposition is being tried but cost remains an issue

pinhead1
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re: Perfecting the 3-D chip
pinhead1   10/13/2011 5:19:05 PM
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Good question. I was working for one of the cutting edge 3D companies a year ago, and at that point, the EDA was more or less non existent. It was just hacking things together manually.

collin0
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re: Perfecting the 3-D chip
collin0   10/13/2011 3:51:45 PM
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I think TI is also developing 3-D IC now. If we have 3-D IC, does it mean that we could see 3-D video on TV, website,mobile phone,tablet,and all other devices which have display terminal?

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