I think that there are still few challenges for 3D IC design:
- How can we test all IC before they are stacked together?
- Most of current 3D IC is limited to memory or sensor only, it takes time to develop complete strategy for stacking real ASIC together
- Wafer handling and KGD becomes nightmare for product engineer
- How can we handle thermal issues?
- 3M approaches may be good solution and we shall see how to apply this for production. However, I don't prefer liquid cooling solution, it is too complicated for implementation
- New 3D chip architecture related with TSV placement will solve the problem with lower cost
- Is new 3D IC EDA tools required or not?
- I prefer hybrid 3D IC design flow, it re-uses most of current ASIC flow with minor modification, it not only reduces the cost but also shortens the design cycle. For example, the multiple die physical verification time can be reduced by 10X or more through minor changes in current flow.
I agree... secondly one must realize that 3D IC design is also a packaging exercise so that needs to be addressed concurrently. Otherwise, there will be costly repititions and try outs of what is manufacturable.
@Colin Johnson: other entities involved in 3D IC standardization is GSA which has been meeting 4 to 6 times a year on this topic, and Si2 Consortium.
IBM's work in 3D IC by stacking is nothing new, definitely not a secret. At CANDE 2010 and also at GSA 3D Standards meeting earlier this year, there were presentations by IBM folks so I am not at all surprised. What surprises me is 3M taking on the challenge to develop a thermal interface material with high conductivity for gaps less than 1um.
My earlier posting on 3D-related article is here:
yes, the TSVs will take up about 15 - 20 % space on a die ( including the bond pads & keep-outs to isolate transistors from stress induced by the TSVs ) but this would be a wash since no large bond pads would be required for wire bonds any more. Because of the short I/O length ( low loss ) and high I/O density possible, TSVs will enable a lot of high - perf / low - power / compact designs.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.