Apple's A5 is a dual core processor & the die size is already 12 x 10 mm. The A6 is a quad core and even at 28 nm would be quite large. The larger the die the lower the yield, especially at the bleeding edge node.
There was a report that TSMC would prefer a multi - chip package for the A6 using Si interposer.
Does anyone know whats pushing TSMC towards that ? What about the A6 at Samsung ?
As i said in the article: fighting in court over smartphone patents and market introductions; supportive buyer-customer relations at the chip level.
One might think it strange that Samsung doesn't just cut Apple off, but if it did that it might damage Samsung's ability to sell chips in the future and its protestations of Chinese Walls between divisions.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.