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Etmax
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re: According to George: The rules dont apply to us
Etmax   11/23/2011 2:48:40 PM
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But isn't the verification part of the design process of the chip, rather than its manufacture? In automotive design the design is designed and verified not unlike a chip design is designed and verified. Aren't we designing parts and process so that volume production is a multiple of the same? The design process happens only once, so that process has to contain significant verification. Maybe I'm missing something here??

Duane Benson
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re: According to George: The rules dont apply to us
Duane Benson   10/31/2011 4:50:35 AM
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Is it possible that the complexity of a big chip is simply beyond the tools of the time? An airplane can have its wing spar tested. It can have FEA performed on fasteners. It can have the shape tested in a wind tunnel or in a simulator. According to the Boeing web site, there are six million parts in a 747 with half being fasteners. The 747 has a pretty good record of having quality designed in as well as a good record of test and inspection. Does it matter that all of the parts are big enough to hold in your hand? Modern CPUs have transistor counts of 3/4 of a billion and up. FPGAs and memory chips get up in to the multiple billions. I can see some functional blocks as being relatively easy to both design quality in and verify after the fact (memory), but other sections, the complexity is just mind-boggling. Design schedules are likely a big factor as well. Designers are far too often simply not given enough days on the calendar to spend the time necessary to design enough quality in at the start.

cdhmanning
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re: According to George: The rules dont apply to us
cdhmanning   10/30/2011 6:40:19 PM
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From 50,000 ft all design domains (ie. automotive, chip, software, bridges) share some characteristics. What differs though is the cost or verification and testing vs the cost of error. It is, however, important to draw the distinction between design testing/verification and per-unit verification testing. Verification of the design of a chip or a new car model is very different to testing each individual chip or car on the line. We can do "unit testing" on everything from cables and bolts to parts of a chip design to software.We can also do integration testing on sub-assemblies of the above. However the cost/value trade off of doing these tests is differenc across different domains. Where the difference shows up is in the cost of a "do over". In software and chip design, the cost of constructing a sub-assembly to test partial assembly is relatively cheap (assuming you can use an FPGA for the chip testing). When building a bridge that is not the case. So while it is interesting to have a look at different ideas and look for opportunities for cross pollenation, it is not a given that they will be beneficial.



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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