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THW
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re: SerDes chip enables integration of multiple video streams
THW   11/30/2011 11:43:01 PM
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Thanks much for raising the question and suggestion. We are continuously investigating how to achieve superior solutions on system level. In terms of power consumption the chipset (serializer and deserializer pair) will consume less than 500mW, which should be around half the power of packet-based solutions when looking at the complete video and control data transport function.

DrFPGA
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re: SerDes chip enables integration of multiple video streams
DrFPGA   11/18/2011 5:55:41 PM
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I don't see any numbers for power consumption. How much additional power does the solution take? Also- it seems like a multi-channel de-serializer would be a nice next step. Is that in the works?



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