Admire the task and the wisdome to jump in this blazing ride, I got a headache of just the thought of the 3D elecromagnetic modeling required. I don't know much about other mediums, but doesn't photo/laser drivers/receivers still need to do a medium exchange to electrical PHY, at a throuput penalty?
I forgot to mention protocol; we used SONET, since that's what the guys designing our ASICS knew best (and it's extremely robust). However, the testing was protocol-less, since there wasn't any HW (besides the experimental "super-LVDS" transceivers that could execute any protocol at those speeds.
I take my hat off to the specification gurus; if you get the protocol right, down to the PHY level, every else's job gets easier. Unterminated short-haul buses like PCI set performance/cost standards where SCSI and VME feared to tread, albeit at a cost of repeat prototype cycles.
I2C still trundles along just fine, but the newer serial buses have to be applauded for their reliability in the most cost-constrained applications. No exotic materials for them, but we all rely on HDMI, SATA and now Thunderbolt delivering unconscionably high data-rates. I often wonder at the contrast between their undoubted performance and the conservative much slower BPs of the past. Were they, in the final analysis, a tad over-engineered?
Clearly, much of the answer lies in the design of fast, advanced analog receivers, rather than in the wiring.
Biggest lessons: Impedance formulas were not consistent, even from the same companies! Etch is trapezoidal in shape, making difficulty in materials and calculations. There are no rules of thumb useable, just be anal. I rederived all the equations, ran it in a spreadsheet. Changing the dimensions found convergence in the accuracy/stability of the impedance match. special Drivers & Receivers, then you'll need that exotic material. Choose well. Many board houses have never cut their teeth on these materials. And maybe, for brevity, everyone, board house & every SW CAD package used must support, at least 1/10,000 of an inch detail, and with the best exotic material, without delamination. Then read an 18" stackup of documents covering this by experts. Best I can offer... until hired ;-)
Mark! Previous Boss, glad to hear from you. Not many bosses speak well of employees after 10 yrs.
I was conservative and driven. There was no minimizing the importance of the Backplane and the importance to the company that it perform to extreme throughput. It required special drivers & receivers, with additional performance features. The BP, I layed out the etch to 1/10,000 of an inch. The geometries converged to drop impedance errors to less than 5%. We used EO TDR equipment to scour the impedance match from card to BP to card. Highest glitches were the connectors. We worked on it together. I think the biggest help was the 3 months wait for Architecture to congeal, allowed me to read a stack of documents on how to design a High Speed BP, that stacked up about 18" off the floor in my office. You might recall the stack. Anyway, good to hear from you!!! I still have my notes in case you want to go solo on this venture. -BB
Blog Doing Math in FPGAs Tom Burke 2 comments For a recent project, I explored doing "real" (that is, non-integer) math on a Spartan 3 FPGA. FPGAs, by their nature, do integer math. That is, there's no floating-point ...