Have seen a few things from Amkor on memory cubes using TSVs. I wonder how much wafer thinning needs to be done to produce these things. 128GB/s is incredible bandwidth, but 10micron thick, or should I say thinned, wafers are incredibly delicate. Test at all levels is also a crucial consideration, but I trust IBM more than most to do a good job.
HMC technology uses advanced TSVs — vertical conduits that electrically connect a stack of individual chips — to combine high-performance logic with Micron’s state-of-the-art DRAM. HMC delivers bandwidth and efficiencies a leap beyond current device capabilities. HMC prototypes, for example, clock in with bandwidth of 128 gigabytes per second (GB/s). By comparison, current state-of-the-art devices deliver 12.8 GB/s. HMC also requires 70 percent less energy to transfer data while offering a small form factor — just 10 percent of the footprint of conventional memory.
This is a good match - because IBM has been working and publishing on 3D stacks using TSVs for at least the last 4 years and their technology would be at least on par with Samsung ( who have been demonstrating 3D DRAM stacks for the last 3 years ).
Micron's recent overtures to Samsung is probably more for generating common standards - which is needed for wider adopton of this technology.
IBM on the other hand would actually fab the controller chip for Micron's HMC module and might do the TSVs for Micro's DRAM and assemble the whole stack.
What is not clear from this report though is if Micron has said anything so far about any long term association with IBM ( e,g. after a trial period license their process and then do HVM in house ? )
Anyone care to comment ? Phil ?
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