Just yesterday I heard a news story here in San Diego about Gordon, the new supercomputer at the local SD Supercomputer Center. It has a 9X speed increase over last year's speed champ due to the use of what were described as 'massive' SSD's for storage. It looks like it will soon be due for an upgrade...
This is from Dan Snyder a PR manager at Intel:
"The smaller cell size enabled by the 20nm litho using the planar cell structure and hi-k metal gate (HKMG) allowed us to double the monolithic die capacity of the previous 25nm generation, where 64Gb was the maximum capacity that could fit in standard memory packaging. The higher dielectric constant of the hi-k enabled the required coupling between the floating gate and the control gate on the 20nm based cell, so the use of HKMG was critical for the production of any capacity NAND on 20nm (both our 64Gb and 128Gb), so therefore HKMG played a critical role in enabling the increase in monolithic die capacity to 128Gb.
To paraphrase -- Intel-Micron needed to use HKMG in the gate-stack to get the 20-nm process to work. So without HKMG they couldn't have done the shrink from 25-nm and got the doubled memory cell density.
I have no idea. But I will ask Intel and Micron on your behalf.
Be prepared. They may say that this is all they wish to say on the topic except to people who are prepared to sign a non-disclosure agreement.
What are the engineering and design challenges in creating successful IoT devices? These devices are usually small, resource-constrained electronics designed to sense, collect, send, and/or interpret data. Some of the devices need to be smart enough to act upon data in real time, 24/7. Are the design challenges the same as with embedded systems, but with a little developer- and IT-skills added in? What do engineers need to know? Rick Merritt talks with two experts about the tools and best options for designing IoT devices in 2016. Specifically the guests will discuss sensors, security, and lessons from IoT deployments.