thank you @agk...static body bias would just shift VTH permanently so it will not solve anything...how would dynamic bias work? low VTH when in operation and high VTH when powered off?...I thought the same trick is used in many processes (like SOI for example)...Kris
My understanding is that the text book challenge to increased leakage current in bulk CMOS is because of the depth of the transistor channel
Like FinFET and FDSOI, DDC has a shallow and tightly controlled channel. Unlike FinFET DDC can support multiple VTs easily.
thank you Peter...low VDD operation requires low VTH...but a textbook challenge of lowering VTH is increased leakage current (it is an exponential increase), perhaps someone from SuVolta can explain how they have overcome that challenge...Kris
I don't think it is made explicit exactly where the work was done. But I think it is safe to assume it was done at a Fujitsu wafer fab or research fab where they can run the 65-nm CMOS manufacturing process.
SuVolta continues to come up with very exciting announcements...but how one develops very advanced transistor structures without access to a state-of-the-art fab?...was the work done at Fujitsu's facilities? Kris
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.