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krisi
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CEO
re: IEDM: SuVolta transistor operates down to 0.4-V
krisi   12/8/2011 3:10:49 PM
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thank you @agk...static body bias would just shift VTH permanently so it will not solve anything...how would dynamic bias work? low VTH when in operation and high VTH when powered off?...I thought the same trick is used in many processes (like SOI for example)...Kris

agk
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re: IEDM: SuVolta transistor operates down to 0.4-V
agk   12/8/2011 9:31:03 AM
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DDC 43 nm needs body bias either fixed or dynamic to make the transitor faster and less leakier.

Peter Clarke
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re: IEDM: SuVolta transistor operates down to 0.4-V
Peter Clarke   12/7/2011 8:05:37 PM
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My understanding is that the text book challenge to increased leakage current in bulk CMOS is because of the depth of the transistor channel Like FinFET and FDSOI, DDC has a shallow and tightly controlled channel. Unlike FinFET DDC can support multiple VTs easily.

krisi
User Rank
CEO
re: IEDM: SuVolta transistor operates down to 0.4-V
krisi   12/7/2011 5:46:00 PM
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thank you Peter...low VDD operation requires low VTH...but a textbook challenge of lowering VTH is increased leakage current (it is an exponential increase), perhaps someone from SuVolta can explain how they have overcome that challenge...Kris

Peter Clarke
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re: IEDM: SuVolta transistor operates down to 0.4-V
Peter Clarke   12/7/2011 5:39:09 PM
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@kris I don't think it is made explicit exactly where the work was done. But I think it is safe to assume it was done at a Fujitsu wafer fab or research fab where they can run the 65-nm CMOS manufacturing process.

krisi
User Rank
CEO
re: IEDM: SuVolta transistor operates down to 0.4-V
krisi   12/7/2011 5:26:03 PM
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SuVolta continues to come up with very exciting announcements...but how one develops very advanced transistor structures without access to a state-of-the-art fab?...was the work done at Fujitsu's facilities? Kris



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