@ChrisGar: After the CMOS imaging Silicon heralded the way for 3D IC, DRAMs are the ones that are leading the way.
WideIO 3D IC standards will be released very soon (stay tuned, there is an article on this by yours truly hitting the portal any minute today). The soon to be released JEDEC standard for this exclusively 3D, though 2.5D version is in the roadmap. This standard explicitly calls for post-stack assembly test enablement.
I'm surprised because it looks like DRAMs will be important for initial 3D IC products. TSMC must be planning to offer their DRAMs as the only DRAM solution for 3D ICs.
Also, testing/DFT is important for 3D ICs. TSMC apparently is prepared to work with customers on test methodology to ensure yield can be optimized, yield learning, burn-in stress, etc.
I think that working with OSATs for the Xilinx 2.5 D module has probably provided TSMC a good gap and risk analyses. The technical drivers behind TSMC decision to do it all may be the fact that when it comes to resolving key integration issues e,g. chip package interaction, thin-wafer handling etc. TSMC probably has a lot more engineering resources than the OSATs themselves. If interested you can look up TSMC papers at recent IEEE - IITC conf.
My question was more what are the global business scenario / tech. contingency ( e,g. trouble at 20 nm ) assumptions under which TSMC thinks this would be a viable alternative for them.
This is not encouraging for small companies and the startups that can innovate for 3DIC-enabled product innovations.
@chipmonk: I am not sure if the business volume from 3DIC products coming TSMC's way (GloFo is actively working on this too!) is enough to offsest any debacles from TSMC's 20nm business. Certainly the announcement above doesn't encourage small companies to go TSMC's way for 3DIC business.
I find the statement "Someone has to come forward to assume the responsibility..." amusing! This has been an on-going debate on who 'owns' the yield issues, reworks (if possible) and I don't believe it is going to be decided any time soon.
Customer are very apprehensive to go to market with a plan that involves brand new chip - chip - package interactions where ownership of issues and development overruns can be critical in time to market and success.
The profit margin for packaging & assembly is just a fraction of that possible even for a Foundry like TSMC. So whats TSMCs motive to keep all 3D in - house and even cut off options by opting for via - first ? Is it just to prevent damage during xfer of partially processed wafers to the OSATs for assembly & damage caused by them to the thinned wafers ? What has been the experience during processing the 2.5D FPGAs for Xilinx ?
Or is it more a business decision ? e,g. keeping everything inside a secret from nosey OSATs. This would only mean that TSMC is really banking on 3D stacking as a way to get off the Moore's Law treadmill in case their 20 nm bombs.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.