Breaking News
Comments
Newest First | Oldest First | Threaded View
docdivakar
User Rank
Manager
re: TSMC goes it alone with 3-D IC process
docdivakar   12/16/2011 6:20:43 PM
NO RATINGS
@ChrisGar: After the CMOS imaging Silicon heralded the way for 3D IC, DRAMs are the ones that are leading the way. WideIO 3D IC standards will be released very soon (stay tuned, there is an article on this by yours truly hitting the portal any minute today). The soon to be released JEDEC standard for this exclusively 3D, though 2.5D version is in the roadmap. This standard explicitly calls for post-stack assembly test enablement. MP Divakar

ChrisGar
User Rank
Rookie
re: TSMC goes it alone with 3-D IC process
ChrisGar   12/15/2011 3:09:39 PM
NO RATINGS
I'm surprised because it looks like DRAMs will be important for initial 3D IC products. TSMC must be planning to offer their DRAMs as the only DRAM solution for 3D ICs. Also, testing/DFT is important for 3D ICs. TSMC apparently is prepared to work with customers on test methodology to ensure yield can be optimized, yield learning, burn-in stress, etc.

chipmonk0
User Rank
CEO
re: TSMC goes it alone with 3-D IC process
chipmonk0   12/14/2011 5:16:18 PM
NO RATINGS
I think that working with OSATs for the Xilinx 2.5 D module has probably provided TSMC a good gap and risk analyses. The technical drivers behind TSMC decision to do it all may be the fact that when it comes to resolving key integration issues e,g. chip package interaction, thin-wafer handling etc. TSMC probably has a lot more engineering resources than the OSATs themselves. If interested you can look up TSMC papers at recent IEEE - IITC conf. My question was more what are the global business scenario / tech. contingency ( e,g. trouble at 20 nm ) assumptions under which TSMC thinks this would be a viable alternative for them.

docdivakar
User Rank
Manager
re: TSMC goes it alone with 3-D IC process
docdivakar   12/14/2011 4:49:28 PM
NO RATINGS
This is not encouraging for small companies and the startups that can innovate for 3DIC-enabled product innovations. @chipmonk: I am not sure if the business volume from 3DIC products coming TSMC's way (GloFo is actively working on this too!) is enough to offsest any debacles from TSMC's 20nm business. Certainly the announcement above doesn't encourage small companies to go TSMC's way for 3DIC business. I find the statement "Someone has to come forward to assume the responsibility..." amusing! This has been an on-going debate on who 'owns' the yield issues, reworks (if possible) and I don't believe it is going to be decided any time soon. MP Divakar

mlamorey
User Rank
Rookie
re: TSMC goes it alone with 3-D IC process
mlamorey   12/13/2011 10:43:49 PM
NO RATINGS
Customer are very apprehensive to go to market with a plan that involves brand new chip - chip - package interactions where ownership of issues and development overruns can be critical in time to market and success.

resistion
User Rank
CEO
re: TSMC goes it alone with 3-D IC process
resistion   12/13/2011 10:17:14 PM
NO RATINGS
Maybe tsmc has to acquire a packaging company.

KB3001
User Rank
CEO
re: TSMC goes it alone with 3-D IC process
KB3001   12/13/2011 9:28:15 PM
NO RATINGS
Bold move by TSMC.

chipmonk0
User Rank
CEO
re: TSMC goes it alone with 3-D IC process
chipmonk0   12/13/2011 9:22:07 PM
NO RATINGS
The profit margin for packaging & assembly is just a fraction of that possible even for a Foundry like TSMC. So whats TSMCs motive to keep all 3D in - house and even cut off options by opting for via - first ? Is it just to prevent damage during xfer of partially processed wafers to the OSATs for assembly & damage caused by them to the thinned wafers ? What has been the experience during processing the 2.5D FPGAs for Xilinx ? Or is it more a business decision ? e,g. keeping everything inside a secret from nosey OSATs. This would only mean that TSMC is really banking on 3D stacking as a way to get off the Moore's Law treadmill in case their 20 nm bombs.



EE Life
Frankenstein's Fix, Teardowns, Sideshows, Design Contests, Reader Content & More
Max Maxfield

Creating a Vetinari Clock Using Antique Analog Meters
Max Maxfield
33 comments
As you may recall, the Mighty Hamster (a.k.a. Mike Field) graced my humble office with a visit a couple of weeks ago. (See All Hail the Mighty Hamster.) While he was here, Hamster noticed ...

EDN Staff

11 Summer Vacation Spots for Engineers
EDN Staff
11 comments
This collection of places from technology history, museums, and modern marvels is a roadmap for an engineering adventure that will take you around the world. Here are just a few spots ...

Glen Chenier

Engineers Solve Analog/Digital Problem, Invent Creative Expletives
Glen Chenier
11 comments
- An analog engineer and a digital engineer join forces, use their respective skills, and pull a few bunnies out of a hat to troubleshoot a system with which they are completely ...

Larry Desjardin

Engineers Should Study Finance: 5 Reasons Why
Larry Desjardin
45 comments
I'm a big proponent of engineers learning financial basics. Why? Because engineers are making decisions all the time, in multiple ways. Having a good financial understanding guides these ...

Flash Poll
Top Comments of the Week
Like Us on Facebook
EE Times on Twitter
EE Times Twitter Feed

Datasheets.com Parts Search

185 million searchable parts
(please enter a part number or hit search to begin)