@dnandy, thanks for the interesting comments. I can understand how a dedicated hardware architecture results in better efficiency (i.e. performance improvement), but I am not clear as to how power consumption is reduced. e.g. we are comparing power consumption for gesture recognition between the MM-3101 and an ARM Cortex A9.
This is a comment to both.Image understand tasks require 2-D area based image processing, best applied using vector processors and data-flow architectures. Doing this is SW really reduces it multiple for loop structures, which consume cycles and power. A dedicated data-flow vector processing pipeline can do it efficiently at lower power. The key is to balance the HW flexibility so that programability is not impacted
I suspect that this will either be a short-lived product or end up only in niche applications. The next generation of processors will likely have enough horsepower to do the same tasks in software without a significant performance hit.