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t.alex
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re: CES: Ceva recognizes gestures with new core
t.alex   1/8/2012 12:33:12 AM
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I think they target mobile devices so speed needs to be fast while poweef needs to be low.

para723
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re: CES: Ceva recognizes gestures with new core
para723   1/7/2012 4:30:36 AM
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@dnandy, thanks for the interesting comments. I can understand how a dedicated hardware architecture results in better efficiency (i.e. performance improvement), but I am not clear as to how power consumption is reduced. e.g. we are comparing power consumption for gesture recognition between the MM-3101 and an ARM Cortex A9.

goafrit
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re: CES: Ceva recognizes gestures with new core
goafrit   1/6/2012 2:14:53 PM
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It is about footprints. It can take same power to power ten chips when you can have them in one chip.

goafrit
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re: CES: Ceva recognizes gestures with new core
goafrit   1/6/2012 2:14:06 PM
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Power and area - monolithin chip gives you better value in power and integration

krisi
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re: CES: Ceva recognizes gestures with new core
krisi   1/5/2012 9:36:19 PM
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thank you @dnandy, can you tell how much power can be saved this way? Kris

dnandy
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re: CES: Ceva recognizes gestures with new core
dnandy   1/5/2012 8:56:48 PM
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This is a comment to both.Image understand tasks require 2-D area based image processing, best applied using vector processors and data-flow architectures. Doing this is SW really reduces it multiple for loop structures, which consume cycles and power. A dedicated data-flow vector processing pipeline can do it efficiently at lower power. The key is to balance the HW flexibility so that programability is not impacted

Duane Benson
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re: CES: Ceva recognizes gestures with new core
Duane Benson   1/5/2012 6:52:44 PM
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I suspect that this will either be a short-lived product or end up only in niche applications. The next generation of processors will likely have enough horsepower to do the same tasks in software without a significant performance hit.

krisi
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re: CES: Ceva recognizes gestures with new core
krisi   1/5/2012 3:31:26 PM
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Why does gesture recognition require dedicated silicon? Can't this be done in DSP or microprocessor? Kris



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As data rates begin to move beyond 25 Gbps channels, new problems arise. Getting to 50 Gbps channels might not be possible with the traditional NRZ (2-level) signaling. PAM4 lets data rates double with only a small increase in channel bandwidth by sending two bits per symbol. But, it brings new measurement and analysis problems. Signal integrity sage Ransom Stephens will explain how PAM4 differs from NRZ and what to expect in design, measurement, and signal analysis.

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