Trailing edge geometries have always accounted for the bulk of wafer revenues. It's the classic technology adoption life cycle curve. I do think that the early adopters may be getting smaller. You need a very high volume product to afford to go out early in the new technology nodes. But because the volumes are high, from the foundry side of things,it may make up for the fewer number of early adopters.
Not a cheerful message to start the new year!
@Peter Clarke: what is TSMC's plausible explanation for the margin erosion? (...fourth quarter revenue decreased 4.9 percent while net income decreased 22.5 percent). I did not see any major TSMC announcements on Capex investments in Q4 2011 so I am a bit surprised about the net income drop.
What is also noteworthy is their statement on "...trailing edge geometries accounted for 41 percent of wafer revenues..." seems to me that many TSMC clients are postponing migration to advanced nodes.
As we unveil EE Times’ 2015 Silicon 60 list, journalist & Silicon 60 researcher Peter Clarke hosts a conversation on startups in the electronics industry. Panelists Dan Armbrust (investment firm Silicon Catalyst), Andrew Kau (venture capital firm Walden International), and Stan Boland (successful serial entrepreneur, former CEO of Neul, Icera) join in the live debate.