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PV-Geek
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re: TSMC process in trouble, says analyst
PV-Geek   2/11/2012 10:02:44 PM
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Regardless of the truth of the details, 28nm has been a real challenge, particularly in the initial ramp up phase. This is more sanely evidenced in the increasing amount of DFM activities being pushed to the designer at these nodes. Things like litho checking, smart fill, pattern based checks, and restricted design rule checks have migrated from recommended to required. This is evidence enough that many of the second and third order effects on yield are becoming first order. Strict adherence and effort spent optimizing these DFM issues in the design phase is probably what is causing such different results on different chips. All designs are not the same from a DFM perspective.

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